Karegoud Lawanya

Software Engineer

Hyderabad, Telangana, India10 mos experience

Key Highlights

  • Expert in Physical Design and SoC methodologies.
  • Strong foundation in RTL Design and Computer Architecture.
  • Teaching Assistant experience at a prestigious institute.
Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in ASIC and SoC development.

Contact

LinkedIn

Skills

Core Skills

Physical Design FlowSystem On A Chip (soc)

Other Skills

Static Timing AnalysisRISC-VRTL DesignRTL to GDS FlowProcessor DesignDSOCadence VirtuosoVerilogComputer ArchitectureStructural ModellingISAClock Domain CrossingSynchronisersFIFOCMU-BDD Package

Experience

10 mos
Total Experience
10 mos
Average Tenure
10 mos
Current Experience

Nvidia

ASIC Physical Design Engineer

Jul 2025 – Present · 10 mos

Static Timing AnalysisPhysical Design FlowRISC-VSystem on a Chip (SoC)RTL DesignRTL to GDS Flow+20

Indian institute of technology, bombay

Teaching Assistant

Aug 2023 – Apr 2025 · 1 yr 8 mos

Education

Indian Institute of Technology, Bombay

M.tech — Electronic systems

Jun 2023 – May 2025

National Institute of Technology, Kurukshetra, Haryana

Bachelor of Technology - BTech — ece

Jan 2019 – Jan 2023

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