Gokul S — Product Engineer
->Proficient in System Verilog(SV) ->Skilled in Universal Verification Methodology(UVM) ->Skilled in writing and implementing block and System level Test cases
Stackforce AI infers this person is a Design Verification Engineer with expertise in VLSI and System Verilog.
Location: Bangalore Urban, Karnataka, India
Experience: 6 yrs 8 mos
Career Highlights
- Proficient in System Verilog and UVM.
- Skilled in writing and implementing test cases.
- Experienced in design verification engineering.
Work Experience
Samsung Semiconductor India
Contractor (3 yrs 1 mo)
Excelmax Technologies
Senior Design Verification Engineer (3 yrs 1 mo)
AMD
Contractor (1 yr 8 mos)
App-Ex Semiconductor Pvt Ltd
Design Verification Engineer (2 yrs 1 mo)
Maven Silicon
Project Intern (1 yr 5 mos)
Education
Bachelor of Engineering - BE at Tamilnadu College of Engineering
vlsi design and verification trainee at Maven Silicon
