Divya Nakerakanti

Software Engineer

Bengaluru, Karnataka, India2 yrs 7 mos experience

Most Likely To Switch

Key Highlights

Experienced in RTL to GDSII flow in semiconductor design.
Proficient in static timing analysis and low-power design.
Hands-on experience with Synopsys tools for digital design.

Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in digital circuit design and timing analysis.

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Skills

Core Skills

Static Timing AnalysisLow-power DesignGlobal Distribution Systems (gds)

Other Skills

Prime timePlacementFloorplanningDesign Rule Checking (DRC)Digital DesignsSynopsys IC CompilerTimingRTL DesignLayout VerificationEDATiming ClosureDigital Circuit DesignRoutingClock Tree SynthesisTCL

Experience

2 yrs 7 mos

Total Experience

1 yr 3 mos

Average Tenure

2 yrs 2 mos

Current Experience

Qualcomm

Engineer

Mar 2024 – Present · 2 yrs 2 mos · On-site

Indian institute of technology, guwahati

Project Scientist

Oct 2023 – Mar 2024 · 5 mos

Static Timing AnalysisLow-power Design

Intel corporation

Intern

Aug 2022 – Jul 2023 · 11 mos · Hyderabad, Telangana, India

Hands on experience in block level implementation (RTL to GDSII) flow starting from synthesis to finish.
 Manual placement of macros around periphery of the core by understanding the data flow fly-lines.
 Achieving congestion-free placement by iteratively changing the floorplan for better routing and standard cell utilization.
 PnR implementation of design using Synopsys Fusion compiler. Understanding the design
requirement and providing the right constraints for each stage to achieve the best possible QOR.
 Worked with Prime-Time tool for static timing analysis (STA) to meet setup, hold timing
requirements after analyzing timing reports.

Global Distribution Systems (GDS)Prime timeStatic Timing Analysis