Vishal Topiya

Software Engineer

Bengaluru, Karnataka, India15 yrs 6 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Expert in VLSI design and verification methodologies.
Proven experience in Bluetooth IP development.
Strong background in FPGA-based digital system design.

Stackforce AI infers this person is a VLSI and FPGA design expert in the semiconductor industry.

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Skills

Core Skills

Vlsi DesignVerificationFpga Design

Other Skills

UVMOVMSystem VerilogBluetooth IP developmentBluetooth IPDSP ApplicationsTechnical writingHDL CodingTestingVerilogUniversal Verification Methodology (UVM)Open Verification MethodologyCadence IESsimvisionNCSim

About

Currently working as a Pre Si Validation Engineer at Intel Technology India Pvt. Ltd., Bangalore. Previously worked as a Senior Verification Engineer at AMD India Pvt. Ltd. from Cerium Systems (Sep. 2016 - Feb.2018), Senior Engineer at Mindtree (Sep.2013 - Aug.2016) and Senior R&D Engineer at Venus Technologies(July2012 - Aug.2013). The highest degree earned is M.Tech with VLSI and Embedded system specialization from Dhirubhai Ambani Institute of Information and Communication Technology (DA-IICT). Qualified GATE two times in 2010 and in 2011 with the highest GATE score of 611 and All India Rank (AIR) of 1581 in GATE-2010 in Electronics and Communication stream. Bachelor of Engineering is done from Maharaja Sayajirao University of Baroda, One of the best Universities in Gujarat with the specialization in Electronics. The technical area of interest are VLSI design and Verification Digital System Prototyping on FPGA Non-technical area of interest are Playing cricket, Badminton, Table tennis and Chess Reading Inspiring books Watching movies and cricket match Listening soft music Skills: Digital IP Verification using SV and Methodology, Complete IP design cycle starting from specification understanding to it's prototype on custom FPGA board

Experience

15 yrs 6 mos

Total Experience

2 yrs 5 mos

Average Tenure

8 yrs 4 mos

Current Experience

Intel corporation

Design Verification Engineer

Feb 2018 – Present · 8 yrs 4 mos · Bengaluru, Karnataka, India · Hybrid

Amd

Senior Verification Engineer - Contingent

Nov 2016 – Jan 2018 · 1 yr 2 mos · Bengaluru Area, India

Worked as a Senior Verification Engineer at AMD India Pvt. Ltd.

Mindtree

2 roles

Module Lead

Jan 2016 – Aug 2016 · 7 mos

Worked as a Module lead while working with BLE IP development team.

Senior Engineer

Sep 2013 – Dec 2015 · 2 yrs 3 mos

Worked as a Senior Engineer in VLSI design and Verification domain. Worked as a team player with Verification team responsible for Verifying and developing various VIP using Methodologies like UVM, OVM and System Verilog. Also worked with a Bluetooth IP development team for design, verification and validation of Bluetooth IP versions 4.1, 4.2 and 5.0.
Protocol knowledge : UART, SPI, AHB

VLSI designVerificationUVMOVMSystem VerilogBluetooth IP development

Venus technologies

Senior R&D Engineer

Jul 2012 – Aug 2013 · 1 yr 1 mo · Bengaluru Area, India

Here I have worked as a Senior R&D Engineer in hardware domain. I needed to deal
with the projects of VLSI design, DSP Applications, FPGA based digital system design etc..
Responsibilities here include Technical writing, HDL Coding, Testing and Verification of digital
design on FPGA and Research gap analysis.

VLSI designDSP ApplicationsFPGA designTechnical writingHDL CodingTesting+1

Dhirubhai ambani institute of information and communications

M.Tech Student and Teaching Assistant

Jul 2010 – May 2012 · 1 yr 10 mos

Research topic for M.Tech was Carrier recovery in Software Defined Radio (SDR). Detail about this topic is mentioned in the project section.
TEACHING ASSISTANTSHIP
TA for ‘Business Management’ under Prof. Nikhil Raval. (July 2010 - December 2010)
TA for ‘Analog Circuits’ under Prof. Subhajit Sen. (January 2011 – April 2011)
TA for ‘Principal of Management’ under Prof. Soumitra Banerjee. (July 2011 – December 2011)
TA for ‘Digital Logic Design’ under Prof. Mazad Zaveri. (January 2012 – April 2012)

Da-iict

Teaching Assistant

Jul 2010 – Apr 2012 · 1 yr 9 mos

TA for ‘Business Management’ under Prof. Nikhil Raval. (July 2010 - December 2010)
TA for ‘Analog Circuits’ under Prof. Subhajit Sen. (January 2011 – April 2011)
TA for ‘Principal of Management’ under Prof. Soumitra Banerjee. (July 2011 – December 2011)
TA for ‘Digital Logic Design’ under Prof. Mazad Zaveri. (January 2012 – April 2012)

Delemer products ltd

service engineer

Jul 2009 – Oct 2009 · 3 mos

The Delmer Group is an internationally renowned name in E-Weighing covering diverse sectors in the Weighing Technology and Jewellery manufacturing Machines. I was working as a service engineer for E-Weighing, Coin Operated Machines and Jewellery Machines.