Varun Jothish

Software Engineer

Bangalore, Karnataka, India16 yrs experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Expert in Physical Design and Integrated Circuit Design.
  • Proven experience in LVS and DRC rule deck development.
  • Strong background in Semiconductor industry with extensive tool knowledge.
Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in Physical Verification and Integrated Circuit Design.

Contact

LinkedIn

Skills

Core Skills

Physical DesignIntegrated Circuit DesignPhysical VerificationRule Deck Development

Other Skills

LVSIC ValidatorDRCLayout VerificationSemiconductor IndustryVLSIPerlPSpiceCMicroelectronicsASICSemiconductorsLayout Versus Schematic (LVS)Very-Large-Scale Integration (VLSI)Design Rule Checking (DRC)

Experience

16 yrs
Total Experience
3 yrs 2 mos
Average Tenure
8 yrs 8 mos
Current Experience

Qualcomm

3 roles

Senior Staff Engineer

Promoted

Dec 2024 – Present · 1 yr 5 mos

LVSIC ValidatorDRCLayout VerificationPhysical DesignSemiconductor Industry+12

Staff Engineer

Dec 2019 – Nov 2024 · 4 yrs 11 mos

Lead Engineer

Aug 2017 – Nov 2019 · 2 yrs 3 mos

Synopsys inc

2 roles

Senior Product Engineer

Jun 2016 – Jul 2017 · 1 yr 1 mo

Product Engineer

Nov 2013 – Jun 2016 · 2 yrs 7 mos

  • Physical Verification CAE in Design Group
  • Develop Rule Deck for LVS & DRC for leading foundries like Samsung, Global Foundries.
  • Two + years of experience in rule deck development for foundries.
  • Responsible for LVS rule deck development for Samsung's 10nm,14nm,28nm process nodes.
  • Experience in Parasitic Extraction QA/STARRC.
  • Specialties: Physical Verification and extraction,PEX qualification, PERL Scripting.
  • Synopsys Tools: ICV, STARRC.
Physical VerificationPEX qualificationPERL ScriptingICVSTARRCRule Deck Development

Kla-tencor

Applications Development Engineer

Jul 2012 – Oct 2013 · 1 yr 3 mos · Chennai Area, India

  • Application Engineer in Wafer Inspection Team

Intel india technology pvt ltd

Analog Circuit Design-Intern

Jun 2011 – Jun 2012 · 1 yr · Bengaluru Area, India

  • Analog Circuit Design Engineer

Tata consultancy services

Assistant Systems Engineer

Oct 2008 – Mar 2010 · 1 yr 5 mos · Ahmedabad Area, India

  • Worked as Assistant Sytems Engineer in TCS.

Education

Manipal Institute of Technology

Master's Degree — Microelectronics

Jan 2010 – Jan 2012

University of Kerala

Btech — Electronics And Communication

Jan 2004 – Jan 2008

Arya Central School

High School — Science

Jan 1989 – Jan 2004

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