Sai Nitish C.

Product Manager

Bengaluru, Karnataka, India7 yrs 11 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Expert in System-on-Chip design and verification
Proficient in UVM and SystemVerilog methodologies
Strong background in ASIC and VLSI design

Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in ASIC and SoC verification.

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Skills

Core Skills

AsicSocVerificationUvmRtl Design

Other Skills

Interconnect fabric IPPPA analysisSub-system Fabric IP verificationVideo and Audio IP features verificationASIC Verification environmentSystemVerilogFunctional coverageAssertionsTest bench automationReset Synchronizer designClock domain crossing synchronizer RTLSystemVerilog test benchElectronicsVerilogEDA

About

Experienced System-on-Chip Design Engineer with a demonstrated history of working in the semiconductors industry. Skilled in Universal Verification Methodology (UVM), SystemVerilog, Application-Specific Integrated Circuits (ASIC), Electronics, and Perl. Strong engineering professional with a Bachelor of Technology (B.Tech.) focused in Electronics and Communications Engineering from Jawaharlal Nehru Technological University.

Experience

7 yrs 11 mos

Total Experience

3 yrs 11 mos

Average Tenure

6 yrs 6 mos

Current Experience

Intel corporation

Design Application Engineer

Dec 2019 – Present · 6 yrs 6 mos · Bengaluru, Karnataka

Working on Interconnect fabric IP.
Responsible for product enablement & PPA analysis of customer designs.

Interconnect fabric IPPPA analysisASICSoC

Amd

Senior Verification Engineer

Apr 2016 – Dec 2019 · 3 yrs 8 mos · Bengaluru, Karnataka

Worked on Sub-system Fabric IP verification which acts a bridge between Cache and Memory controller.
Worked on verification of Video and Audio IP features at SoC level.

Sub-system Fabric IP verificationVideo and Audio IP features verificationVerificationSoC

Ensilica limited

ASIC Verification Engineer

Oct 2014 – Mar 2016 · 1 yr 5 mos · Bengaluru Area, India

Implemention of ASIC Verification environment.
Development of block and system-level verification environments using SystemVerilog, UVM verification languages.
Implemention of functional coverage and assertions using System Verilog.
Development of test bench automation, regression and other verification enhancements to improve productivity.
Development of Verification test plans, test suites and verification activities.

ASIC Verification environmentSystemVerilogUVMFunctional coverageAssertionsTest bench automation+1

Experthdl

ASIC Design Verification Engineer

Oct 2013 – Sep 2014 · 11 mos · Bengaluru, Karnataka

Implemented the design of Reset Synchronizer in Receiver path to capture the received Serial Data.
Implementation of Clock domain crossing (CDC) synchronizer RTL in the Asynchronous FIFO.
Developed an effective test bench using SystemVerilog.
Verified the RTL with random stimulus and directed testcases for corner scenarios.

Reset Synchronizer designClock domain crossing synchronizer RTLSystemVerilog test benchASICRTL Design