Ramprasad N

Product Manager

Bengaluru, Karnataka, India14 yrs 7 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Over 13 years of DFT engineering experience
Expert in advanced technology nodes from 5nm to 28nm
Proven track record of improving test coverage and reducing costs

Stackforce AI infers this person is a Semiconductor DFT Engineer with extensive experience in test architecture and validation.

Contact

ramprasadmbe@gmail.com LinkedIn

Skills

Core Skills

DftAtpgMbist

Other Skills

DFT strategyscan insertionpost-silicon validationscanXLBISTtest constraintspost-silicon debugtest point insertionscan chain debugJTAG verificationOCP protocolVerilogPERLCVHDL

About

I am a seasoned Design-for-Test (DFT) Engineer with over 13 years of experience in architecting and implementing test solutions across SoC and block-level designs. My expertise spans scan insertion, MBIST, ATPG, and post-silicon validation across advanced technology nodes (5nm, 7nm, 10nm, 28nm). I specialize in driving DFT strategy, collaborating with cross-functional teams, and delivering high-quality, production-ready netlists. My work has consistently improved test coverage, reduced test cost, and accelerated time-to-market. I’ve also contributed to industry knowledge through technical papers and presentations at global DFT forums. I’m passionate about solving complex design challenges and enabling robust, scalable test architectures that support silicon success.

Experience

14 yrs 7 mos

Total Experience

2 yrs 5 mos

Average Tenure

4 yrs 2 mos

Current Experience

Nxp semiconductors

Principal Design Engineer – DFT

Apr 2022 – Present · 4 yrs 1 mo · Bengaluru, Karnataka, India

Spearheaded DFT strategy and execution for SoCs (Helios2, Yukon, Danube) on the 28nm node.
Engineered high-efficiency ATPG patterns, improving test coverage by 8% and reducing test time by 28 seconds.
Automated test point execution, reducing effort from 2 days to 1 hour.
Collaborated with PD, synthesis, and power teams to ensure timely netlist delivery.
Architected AMS DFT using test point registers, Q-gating, and clock staggering to mitigate IR-drop.
Presented technical papers at internal DFT User Meetings, showcasing innovation and leadership.

ATPGDFT strategyscan insertionpost-silicon validationDFT

Qualcomm

Senior Lead Engineer – DFT

Oct 2019 – Mar 2022 · 2 yrs 5 mos · Greater Bengaluru Area

Led Core-Based DFT (CBDFT) initiatives for advanced SoCs (LemansAu, Kodiak, Divar, Cedros) on 5nm and 7nm nodes.
Delivered high-coverage ATPG patterns and optimized test point insertion across 100+ blocks.
Defined and implemented scan, XLBIST, and test constraints to ensure robust testability and manufacturability.
Partnered with PD and synthesis teams to streamline netlist delivery and improve design closure timelines.

ATPGscanXLBISTtest constraintsDFT

Cientra

Technical Lead – DFT

Mar 2016 – Sep 2019 · 3 yrs 6 mos · Bengaluru, Karnataka, India

Directed DFT development for Intel and Samsung projects (Icelake, Lakefield, Monethill) on 10nm and 5nm nodes.
Built end-to-end DFT flows including MBIST implementation and post-silicon debug strategies.
Achieved up to 99% test coverage through strategic test point insertion and ATPG optimization.
Played a key role in silicon bring-up and yield enhancement activities.

MBISTpost-silicon debugtest point insertionDFT

Mirafra technologies

DFT Engineer II

Dec 2014 – Feb 2016 · 1 yr 2 mos · Greater Bengaluru Area

Contributed to Qualcomm’s Lykan project, focusing on ATPG pattern generation and yield recovery analysis.
Supported scan chain debug and fault isolation during post-silicon validation.

ATPGscan chain debugDFT

Synapse design inc.

Project Engineer – DFT

Jul 2012 – Dec 2014 · 2 yrs 5 mos · Bangalore

Delivered scan insertion, ATPG, and JTAG verification for clients including Texas Instruments and Maxim Integrated.
Ensured compliance with P1500 standards and enhanced boundary scan coverage.

scan insertionATPGJTAG verificationDFT

Renesas mobile corporation

Intern trainee

Jul 2011 – Jun 2012 · 11 mos · Bangalore

> Design and verification of OCP protocol and integration in top level ASIC interconnect system.
> Code coverage analysis based verification methodology env bringup.
> Exposure to Verilog, PERL.

OCP protocolVerilogPERL