A

Arnab Saha

Software Engineer

6 yrs 3 mos experience
Highly StableAI Enabled

Key Highlights

  • Over 8 years of experience in VLSI design.
  • Led 10+ successful tape-outs in advanced CMOS technology.
  • Expert in high-speed SerDes and mixed-signal circuits.
Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in analog and mixed-signal circuits.

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Skills

Core Skills

High-speed SerdesAnalog Integrated Circuit DesignMixed-signal Ic Design

Other Skills

Logic SynthesisFunctional VerificationASICVerilog-AMSUVMC++Analog LayoutSPICEDFTCadence SpectreParasitic ExtractionMixed-Signal TestRTL DesignPhysical DesignAI infrastructure

About

Deeply motivated to lead, own and contribute in the analog and mixed-signal circuits domain; leveraging a strong foundation in circuit design, physical design, layout, RTL and AMS verification to enable impactful engineering solutions. Proven track record of over 8+ years, mentoring several cross-functional VLSI teams, partner fabs and IP Vendors, delivering 10+ successful tape-outs (high-speed SerDes, memory, chiplet interconnects, precision analog) in advanced CMOS technology nodes (90nm to 12nm, sub 10nm), driving first pass silicon success and mass production for networking, data-center, wireless and mobile SOCs. Experienced in driving technical program leadership, infrastructure scalability, system integration, reliability engineering, operational readiness, and metrics-driven execution across complex multi-stakeholder environments operating under aggressive schedules and evolving platform requirements. Skillset: ◦ Programming languages: C, C++, MATLAB, Verilog, System Verilog, VHDL, Perl/Shell/TCL, Python, SKILL. ◦ VLSI CAD: HSPICE, RTL Compiler, ANSYS TOTEM (EM/IR), SI/PI, QRC, Cadence Virtuoso, Spectre/X/APS, Calibre, MATLAB, Layout Suite, Xilinx ISE, Xilinx Quartus-II, ModelSim SE/Questa, Synopsys Spyglass, USB 2.0 Analyzer, Lint, CDC, SDC, UPF. ◦ Bus interfaces: PCI, PCIe, AXI/AHB/APB, I2C, ATB, Ethernet, CXL, USB, CAN, LIN. IPs expertise: LDOs, Bandgap references, IREF/VREF, POR, ADC/DACs, PLLs, CDR, Oscillators, General Purpose IOs, Tempsense, SerDes/PHYs, Die to Die interconnect, High-speed IO, Optical TIA, Sensor AFE, VCO/DCO, PFD/TDC, HS-DIV, RX (Equalizer, VGA, Sampler, PI, Deserializer), buck, boost, multiphase DC/DC converters

Experience

6 yrs 3 mos
Total Experience
2 yrs 1 mo
Average Tenure
--
Current Experience

Cadence

Senior Lead Engineer

Oct 2024Sep 2025 · 11 mos · On-site

  • SerDes/IO & clocking - DDR, PCIe, USB2.0 (PLL, timing bath, biasgen); PMIC: LDO, DVS, BGR, load switches
Logic SynthesisHigh-Speed SerDesAnalog Integrated Circuit Design

Mediatek

Senior Engineer II

May 2021Aug 2024 · 3 yrs 3 mos · United States · On-site

  • Design and productization of next generation 112G and 224G SerDes PHYs for MediaTek SOCs on leading-edge CMOS process technology nodes (RX Slicer, CTLE, SkewCal, DFE); multi-rail integration, Buck+LDO, Refgen, PMBus
High-Speed SerDesAnalog Integrated Circuit Design

Ceremorphic, inc.

AMS Design Intern

Nov 2020Apr 2021 · 5 mos · Remote

  • UCIe (QSLink) 64Gbps PHY, TX FIR+Driver, RX Sampler, ILO, Deserializer

Microsoft

Silicon Design Intern - High-Speed PHY/IO Team

May 2020Aug 2020 · 3 mos · Raleigh, NC · Remote

  • RX-AFE for GHz ADC based PAM4 112G SerDes
Functional VerificationHigh-Speed SerDes

Texas instruments

2 roles

Analog IC Systems/ Design & DV Engineer

Jul 2017Aug 2019 · 2 yrs 1 mo · Greater Bengaluru Area

  • High-perfomamce analog signal chain, amplifiers, ADC/DAC, VREF/IREF design, OVP/OCP, multiphase DC/DC PWM, Yield improvement, Test & characterization, customer support, supply chain management, failure analysis & reliability.
ASICVerilog-AMSAnalog Integrated Circuit DesignUVMC++Analog Layout+2

Analog Design/Validation Intern

Mar 2017Jul 2017 · 4 mos · Greater Bengaluru Area

  • High-linearity (>16b), low-noise SAR ADC design
DFTCadence SpectreParasitic ExtractionMixed-Signal Test

Intel labs

Embedded Software Intern

May 2016Aug 2016 · 3 mos · Hybrid

  • Developed the Verilog code of Digital Direct Synthesizer (DDS) for Xilinx Spartan 6 Platform for SDR testing.
RTL DesignPhysical Design

Education

University of Michigan

Master of Science - MS — Electrical Engineering & Computer Science

Jan 2021Present

National Institute of Technology Tiruchirappalli (NIT Trichy)

Bachelor of Technology - BTech

Jan 2013Jan 2017

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