Antriksh Aery — Software Engineer
Experienced Verification Engineer specializing in VIP development and support for Intel-specific processor-to-processor communication protocols and CXL 3.0/3.1/3.2. Strong understanding of cache coherency in multi-socket and shared memory systems, with hands-on expertise in SystemVerilog, UVM, and pre-silicon validation. Also have prior experience in firmware verification, specifically for DDR PHY firmware. Focused on building robust, reusable VIPs to ensure protocol compliance and system-level performance.
Stackforce AI infers this person is a Semiconductor Verification Engineer with expertise in protocol compliance and system performance.
Location: Chandigarh, Chandigarh, India
Experience: 7 yrs 8 mos
Skills
- Cxl
- Universal Verification Methodology (uvm)
Career Highlights
- Expert in CXL protocol development and verification.
- Strong background in cache coherency and memory systems.
- Proficient in SystemVerilog and UVM methodologies.
Work Experience
Siemens EDA (Siemens Digital Industries Software)
Member of Consulting Staff (6 mos)
Lead Member of Technical Staff (1 yr 8 mos)
Synopsys Inc
ASIC Digital Design, Staff Engineer (2 mos)
ASIC Digital Design Engineer, Sr 1 (1 yr)
ASIC Digital Design Engineer II (1 yr 6 mos)
Xilinx
Design Verification Engineer (CONT) (5 mos)
SpicaWorks
Design Verification Engineer (6 mos)
NXP Semiconductors
Design Verification and Automation Engineer (CONT) (1 yr 6 mos)
Sevya Multimedia
Design Verification and Automation Engineer (1 yr 11 mos)
Futurewiz
Verification Engineer Trainee (7 mos)
Education
Bachelor of Technology at Chandigarh Engg College, Landran
