Chetan Sahu — Software Engineer

I'm a passionate VLSI engineer on a mission to empower the future through chips and circuits! Knowledgeable, experienced, and driven by a burning passion for technology, I'm currently carving my path through the exciting world of M.Tech in VLSI at NIT-Goa. This journey started with a solid foundation in Electronics and Communications Engineering at Madan Mohan Malaviya University of Technology, where I honed my analytical skills and communication prowess. But theory alone couldn't satisfy my thirst for the real world. So, I stepped into the bustling telecommunications industry at Huawei, tackling foreign projects with ingenuity and automating router script collection like a tech magician. BGP, ISIS, OSPF? No problem! Live networks? Bring it on! My quest for empowerment then led me to ST Microelectronics, where I delved into the mystical world of synthesis flow with DC Compiler and Redhawk. Here, I embraced the inspiring world of AMBA protocols and even breathed life into circuits, transforming transistors into libraries with a Python script. Remember that summer of transformation at MOTILAL NEHRU NATIONAL INSTITUTE OF TECHNOLOGY? That's where I unlocked the secrets of Verilog and embedded systems, crafting an 8-bit ALU and even conjuring a stopwatch symphony with the 8051 microcontroller. But my story doesn't end there. My toolbox overflows with skills like Verilog, C++, Python, CADENCE Virtuoso, and a thirst for knowledge fueled by deep-dive VLSI training, Excel mastery, and System Verilog expertise. My LinkedIn profile is more than just a resume; it's a window into my passion, my experiences, and my desire to build the future. Connect with me, and let's embark on this tech adventure together! P.S. Don't forget to peek at my B.Tech project on an IoT-based crop protection system. It's a testament to my ingenuity and dedication to using technology for good.

Stackforce AI infers this person is a VLSI and Telecommunications Engineer with expertise in circuit design and network management.

Location: Bengaluru, Karnataka, India

Experience: 3 yrs 3 mos

Skills

Sta Using Primetime
Timing Constraints Manager
Ip Synthesis
Network Monitoring
Bgp
Verilog
Embedded Systems

Career Highlights

Expert in VLSI design and implementation.
Proven track record in international telecommunications projects.
Strong foundation in embedded systems and circuit design.

Work Experience

Synopsys Inc

Senior Application Engineer (2 yrs)

STMicroelectronics

Internship Trainee (1 yr)

Huawei

Telecommunication Engineer (1 yr 3 mos)

MNNIT Allahabad

Training Specialist (1 mo)

Education

Master of Technology at National Institute of Technology, Goa

Bachelor of Technology at Madan Mohan Malaviya University of Technology

INTER at Tagore Public School & College - Allahabad

High School Diploma at TAGORE PUBLIC SCHOOL

Chetan Sahu

Software Engineer

Bengaluru, Karnataka, India3 yrs 3 mos experience

Most Likely To SwitchAI ML Practitioner

Key Highlights

Expert in VLSI design and implementation.
Proven track record in international telecommunications projects.
Strong foundation in embedded systems and circuit design.

Stackforce AI infers this person is a VLSI and Telecommunications Engineer with expertise in circuit design and network management.

Contact

Skills

Core Skills

Sta Using PrimetimeTiming Constraints ManagerIp SynthesisNetwork MonitoringBgpVerilogEmbedded Systems

Other Skills

debugging setup/hold violationstiming convergenceruntime and memory improvementECOsscriptingTCL scriptsPython scriptISISOSPFlive network operationXilinx8051 Microcontrollerk-means clusteringComputer ProgrammingInternational Project Management

About

Experience

3 yrs 3 mos

Total Experience

1 yr 7 mos

Average Tenure

2 yrs

Current Experience

Synopsys inc

Senior Application Engineer

Jun 2024 – Present · 2 yrs

Performed STA using PrimeTime, debugging setup/hold violations, and improving timing convergence on SoC designs for Qualcomm and Samsung.
Helped Qualcomm US team Tape out several designs within a year.
Successful deployment of Timing Constraints Manager (TCM), enabling efficient SDC management and signoff readiness for AMD.
Resolved timing and constraint issues for AMD, and Samsung across MMMC scenarios in PrimeTime.
Drove TCM engagement across global teams, improving constraint quality and timing closure efficiency.
Worked on runtime and memory improvement for several customers and enhanced the runtime performance of designs.
Worked on the PTC to TCM migration for AMD and Apple.

STA using PrimeTimedebugging setup/hold violationstiming convergenceTiming Constraints Managerruntime and memory improvement

Stmicroelectronics

Internship Trainee

Jun 2023 – Jun 2024 · 1 yr · Noida, Uttar Pradesh, India · On-site

Block-Level Design (M85ss):
Performed STA using PrimeTime to validate register-to-register timing.
Fixed timing issues with ECOs and scripting and implementing the changes in INNOVUS.
Conducted advanced timing analysis and ensured timing constraints.
Tools used : PrimeTime, Innovus.
IP Synthesis Framework:
Gained in-depth knowledge of IP synthesis with Design Compiler.
Automated IP synthesis using TCL scripts for various technologies.
Scripts processed RTL, SDC, and technology files.
Tools Used : Design Compiler.
Automation Scripts:
Developed Python script for test vector conversion to SystemVerilog (PKA project).
Wrote Python script to extract power data from RedHawk reports.
SoC Verification:
Gained experience in SoC verification for 2 months.
Learned AMBA protocols (AHB, APB, AXI) for on-chip communication.

STA using PrimeTimeECOsscriptingIP synthesisTCL scriptsPython script

Huawei

Telecommunication Engineer

Jul 2021 – Oct 2022 · 1 yr 3 mos · Bengaluru, Karnataka, India · On-site

Accomplished 3 international projects 2 from Indonesia and 1 from Saudi Arabia.
Automated router data collection for efficient network monitoring.
Configured BGP, ISIS, OSPF for optimal network routing.
Gained hands-on experience in live network operation and maintenance.

network monitoringBGPISISOSPFlive network operation

Mnnit allahabad

Training Specialist

Jun 2019 – Jul 2019 · 1 mo

8-bit ALU schematic and Design is implemented using Verilog via Xilinx software.
The stopwatch was implemented with a 7-segment LED display using a microcontroller 8051.