Bruno Paulo

Product Engineer

Cascais, Lisbon, Portugal6 yrs 11 mos experience

Key Highlights

Expert in high-speed SerDes IP development.
Proficient in advanced EDA tools and automation.
Strong background in analog mixed-signal design.

Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in high-speed protocols and analog mixed-signal systems.

Contact

Skills

Core Skills

SerdesEda (electronic Design Automation)Amplifiers

Other Skills

Design ReviewPAM4/NRZPCIeM-PHYTCLPython

About

Analog Mixed-Signal Senior Design Engineer focused on high-speed SerDes IP development in advanced FinFET nodes. Currently serving as the Design Owner for the Tx Driver block, responsible for the full-custom design flow from specification and schematic design to full verification at the extracted level. Experienced in designing for PAM4 and NRZ architectures across PCIe, USB, and M-PHY protocols. I am proficient in advanced EDA flows (Virtuoso, ADE Assembler, Spectre, PrimeSim) and automation using TCL and Linux, ensuring robust design delivery and providing technical guidance during layout reviews.

Experience

6 yrs 11 mos

Total Experience

Average Tenure

Current Experience

Synopsys inc

2 roles

Analog Design, Sr Engineer

Oct 2023 – Present · 2 yrs 8 mos · Oeiras, Lisbon, Portugal · Hybrid

Analog Mixed-Signal Engineer specializing in high-speed SerDes IP development for cutting-edge SoCs in 3nm FinFET technology.
Design Owner for Tx Driver architectures, responsible for the full design cycle from initial specification and schematic design to post-layout extraction and verification.
Proven experience in PAM4/NRZ signaling for high-speed protocols, including PCIe Gen6 and M-PHY Gear 6 standards.
Proficient in industry-standard EDA tools: Cadence Virtuoso (ADE Assembler/Explorer), Spectre, and PrimeSim.
Design automation expert: utilizing TCL for EDA workflow optimization and Python for advanced data analysis and simulation visualization.
Active participant in layout reviews, ensuring signal integrity and PPA optimization in complex 3nm architectures.

SerDesDesign ReviewPAM4/NRZAmplifiersEDA (Electronic design automation)

Master's Thesis | Synopsys & UNL

Mar 2023 – Sep 2023 · 6 mos · Oeiras, Lisbon, Portugal · Hybrid

Developed an AC-coupled shunt regulator in 16nm FinFET technology to enhance the PSRR of a Low-Dropout regulator.
Implemented programmable capacitor banks to improve power supply rejection specifically at medium frequencies.
Designed control mechanisms to ensure the shunt regulator could be toggled without affecting the core LDO performance.

Amplifiers

Grupo procme

Student Internship

Jul 2021 – Jul 2021 · 0 mo · Oeiras, Lisboa, Portugal

Participated in technical site visits to solar and wind power plants to observe large-scale renewable energy operations and maintenance procedures.
Gained introductory exposure to PVsyst and Aurora Solar for the basic simulation and sizing of photovoltaic systems.

Self employed

Mathematics and Physics Tutor

Nov 2018 – Feb 2023 · 4 yrs 3 mos · Estoril, Lisbon, Portugal

Provided academic support and private tutoring in Mathematics for students ranging from high school to university levels, operating across various schools and study centers within my residential area.
Developed strong communication and pedagogical skills through teaching diverse groups, which helped my current ability to provide and receive clear technical support and design guidance to colleagues at Synopsys.