Jose Martin Saji

Software Engineer

Bengaluru, Karnataka, India4 yrs 4 mos experience

Most Likely To Switch

Key Highlights

Expertise in VLSI design and automation.
Proficient in PCIe and physical design methodologies.
Strong problem-solving skills in customer-facing roles.

Stackforce AI infers this person is a VLSI engineer with expertise in semiconductor design and automation.

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Skills

Core Skills

Very-large-scale Integration (vlsi)PcieVlsi AutomationRegression FrameworkPhysical DesignVlsiSoftware DevelopmentCustomer Support

Other Skills

System VerilogTcl ScriptingXilinx VivadoUniversal Verification Methodology (UVM)FloorplanningC++ASP.NET MVCCustomer ExperienceCustomer EngagementWaveform DebugSynthesis FlowCXLRTL DebugEDA Tool flowPython

About

I am a VLSI enthusiast with a Master of Technology in VLSI Design from Vellore Institute of Technology, where I gained strong fundamentals and zeal to learn more in the field. Open to discussions, opportunities, challenges and projects which involve advancements in VLSI.

Experience

4 yrs 4 mos

Total Experience

1 yr 5 mos

Average Tenure

2 yrs 2 mos

Current Experience

Synopsys inc

Applications Engineering, Sr Engineer

Apr 2024 – Present · 2 yrs 2 mos · Bengaluru, Karnataka, India · On-site

Responsible for ensuring Synopsys IP products meet quality targets. Currently working in the PCIe/CXL India AE team. Works closely with various IP applications and R&D engineering teams to ensure smooth out-of-the-box experience for Synopsys Interface IP customers. Working on the PCIe Gen6 and Gen7 SNPS products, helping customer to integrate the IP in their SoC and helping with any issues they face doing so.

System VerilogPCIeVery-Large-Scale Integration (VLSI)

Taltech technologies pvt. ltd.

VLSI Automation Engineer- Regression- Client(AMD)

Oct 2023 – Apr 2024 · 6 mos · Hyderabad, Telangana, India · On-site

1. Owning the regression framework and develop/maintain the flow framework.
2. Analysing the testcases in regression for IP and reporting it back to the IP owner and EDA tool team.
3. Will be responsible to analyse and triaging Vivado regression failures, includes quality bug reporting using Jira.
4. Deliver on release convergence activities of the Vivado EDA tool.

Tcl ScriptingXilinx VivadoVLSI AutomationRegression Framework

Nvidia

ASIC Intern

Aug 2022 – Jun 2023 · 10 mos · Bengaluru, Karnataka, India · On-site

As a Block owner, I am responsible for completing all the tasks in the RTL to GDSII flow, which includes:
1. Block level floor planning
2. Placement and optimization (Congestion analysis and improvement)
3. Clock Tree Synthesis and Skew Balancing
4. Routing and optimization
5. Complete physical verification (DRC/ERC/ANT/LVS)
6. Static Timing Analysis and ECO implementation
7. TCL scripting for PD automation
Tool Experience
Physical design : IC Compiler II (Synopsys), Innovus (Cadence)
Have used TCL to automate tasks within the EDA tool to enhance the design and fix issues in the design.

Universal Verification Methodology (UVM)FloorplanningPhysical DesignVLSI

Tata consultancy services

Assistant System Engineer

Jan 2020 – Sep 2021 · 1 yr 8 mos · India

Work closely with product management to ensure unit in product support. Performed diagnostics to isolate and determine cause of software performance problems and malfunctions. Solving problems raised by the customers in a timely manner.

C++ASP.NET MVCSoftware DevelopmentCustomer Support