May 2026 – May 2026 · 0 mo · Bengaluru, Karnataka

• Change in career path

Aug 2023 – Apr 2026 · 2 yrs 8 mos · Bengaluru · On-site

• Maintaining sign-off checks and CAD automation flows, focusing on asynchronous structural checks and a small part of timing scripts
• Exploring and developing different newer checks like clock path reconvergence, synchronizer standard cell usage review, exception review for glitches, etc., for signoff as chip complexity increases and newer project requirements
• Creating an automated flow for identification of structural glitches on datapaths and controlpaths in post-synthesised netlist. Flow development, QoR analysis, regression, and deployment for projects. Identified 2 glitch bugs on a custom datapath interface with the flow in a recent project. Participated in internal technical submissions
• Developing mapping and correlation automation flow for RTL to netlist transformation and CDC violation correlations, waiver porting mechanisms from RTL to Netlist using synthesis and formality output files like unloaded, undriven, merged flop report, constant optimised flop report, fmdiff mapping log, etc. Ported around 15 million CDC waivers for a recent project
• Maintaining internal flow related scripts (TCL, perl, python, bash) and regressions
• Familiarity with Verilog for debugging CDC-related violations in RTL files
• Ensuring smooth and faster execution for implementation/execution teams with continuous support and communication
• Execution and signing off on structural async checks, including CDC, glitch and reconvergence on post-synthesis netlist of 3 SoC projects and testchips with more than 200 clocks
• Managing generic timing constraints (SDC), exceptions and waivers for clock propagation, constraining and waiving CDC paths, blocking structural glitch propagation, etc.
• Identified 10 structural bugs in netlist & constraints which were fixed with custom scripts & ECO, along with methodology improvements by taking continuous feedback from IP owners for signoff at different milestones of the 3 projects

Jul 2022 – Jun 2023 · 11 mos · Hybrid

• Ramping up on Clock Domain Crossing concepts, methodologies and flows
• Developing check flows for identification of structural glitches in design in post synthesized netlist
• Collaborating with IP teams in understanding differences in structural violations between RTL and netlist

Mar 2021 – May 2021 · 2 mos · India

• Electrical Engineer

Nov 2020 – Jun 2021 · 7 mos · Kolkata Area, India

• Patch deployment activities for tcs bancs software releases