Krishna Thakkar

Software Engineer

Pune District, Maharashtra, India5 yrs experience

Key Highlights

Expert in RTL design and microarchitecture planning.
Proven track record in functional debugging and lint cleanup.
Hands-on experience with Ethernet PHY and USB Controller IP.

Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in RTL and microarchitecture.

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Skills

Core Skills

MicroarchitectureCdcRtl DesignUsb

Other Skills

RTL CodingVerilogUniversal Verification Methodology (UVM)Ethernet PHYEthernetAXILintFpgaModelSimFunctional DebuggingPerforceLintingWritten CommunicationCommunicationSystemVerilog

About

RTL Design Engineer with 3+ yrs of experience specialized in microarchitecture planning, RTL design, functional debugging along with lint cleanup, and CDC analysis for complex PHY and Controller IP designs. Skilled in Verilog/SystemVerilog, with hands-on experience in Ethernet PHY IP - 10BT1S and USB Controller IP . Languages: Verilog, SystemVerilog EDA Tools: Synopsys VCS, Verdi, Spyglass, VCSpyglass, VCFormal, Design Compiler, DVE, Quartus IDE, Modelsim Interface Protocols: USB, AHB, Ethernet - 10BT1S Skills: RTL Design, Microarchitecture, Functional Debugging, Lint, Clock Domain Crossing (CDC)

Experience

5 yrs

Total Experience

Average Tenure

Current Experience

Synopsys inc

3 roles

ASIC Digital Design, Sr Engineer

Promoted

May 2026 – Present · 1 mo

Worked on MicroArchitecture Development of Topology Discovery Feature for Ethernet 10BT1S PHY.
Implemented CSRs , TX path logic along with the enhancements in XCVR driver to add support for Topology Discovery Feature
Implemented CDC-safe synchronizers for control and data signals across multiple clock domains, ensuring reliable
cross-domain communication.
Implemented functional safety enhancements including one-hot FSM protection, FSM timeout protection
aligned with ISO 26262 requirements.

MicroarchitectureCDC

ASIC Digital Design Engr

Jun 2023 – May 2026 · 2 yrs 11 mos

Owned RTL fixes and functional debugs for USB2.0 and USB3.x IP along with maintaining the quality metrics for multiple production
releases.
Debugged simulation failures with root-cause analysis, isolating RTL vs testbench issues across protocol logic, clock/reset
sequencing, and low-power scenarios.
Implemented synthesis-safe RTL fixes validated through regression and Logical Equivalence Checks (VCFormal), ensuring
functional correctness along with documentation.
Resolved lint and CDC violations using Spyglass/VCSpyglass and collaborated across design, verification, and applications
teams to close several customer issues.

RTL CodingUSBRTL Design