shankar kumar yadav — Software Engineer
I am an experienced SOC (System-on-Chip) Design Engineer with 10+ years of expertise. I excel in SOC architecture, RTL design (Verilog/SystemVerilog), ASIC/FPGA design, and robust verification. My skills include firmware development, low-power design, simulation/emulation, and cross-functional collaboration. I manage projects effectively, ensuring on-time deliveries. Proficient in analog/digital circuit design, IP integration, debugging, scripting (Python/Perl), and SystemVerilog/VHDL. I'm well-versed in embedded processors, clock/power management, and industry standards. Continuous learning, problem-solving, and meticulous documentation are integral to my approach. I prioritize compliance, security, and safety, making me a valuable asset to SOC design teams, delivering cutting-edge solutions. SOC Architecture: I possess a deep understanding of SOC architecture, allowing me to seamlessly integrate various IP blocks, memory subsystems, and peripherals to create cohesive, high-performance solutions. RTL Design: My proficiency in RTL (Register Transfer Level) design using Verilog and SystemVerilog ensures robust and efficient hardware implementations. ASIC and FPGA Design: I excel in ASIC and FPGA design methodologies, from the initial concept to the final tape-out or bitstream generation, delivering reliable and high-performance chips. Firmware Development: My experience extends to firmware and embedded software development, enabling smooth hardware-software co-design and functionality. Low Power Design: I am well-versed in low-power design techniques, ensuring optimal power efficiency while meeting performance targets in SOC designs. Simulation and Emulation: Proficiency in industry-standard simulation tools and emulation platforms allows me to perform pre-silicon validation and performance analysis efficiently. Cross-functional Collaboration: Effective communication and teamwork skills enable me to collaborate seamlessly with hardware engineers, software developers, and system architects to drive projects to successful outcomes. IP Integration: I have successfully integrated third-party IP cores and custom IP blocks into SOC designs, enhancing functionality and reducing development time. Debugging Skills: Strong debugging skills enable me to quickly identify and resolve hardware and software issues during SOC development, minimizing project delays. Scripting and Automation: Proficiency in scripting languages like Python and Perl facilitates automation, streamlining design and verification tasks for increased efficiency.
Stackforce AI infers this person is a highly skilled SOC Design Engineer with expertise in FPGA and ASIC design.
Location: Bengaluru, Karnataka, India
Experience: 11 yrs 5 mos
Skills
- Soc Design
- Rtl Design
- Fpga Design
Career Highlights
- Over 10 years of SOC design experience.
- Expert in RTL design and verification methodologies.
- Proficient in low-power design techniques.
Work Experience
Synopsys Inc
SoC Design Engineer (3 yrs 10 mos)
Staff Engineer soc design (3 yrs 10 mos)
Capgemini Engineering
RTL Design engineer at Capegemini Consulting India Private Limited (4 yrs 2 mos)
Space Applications Centre, ISRO
RTL Design Engineer (10 mos)
Indian Institute of Technology, Bombay
Project assitant (1 yr 3 mos)
five core electronics ltd ,delhi
RTL design engineer (1 yr 4 mos)
Education
Master of Technology - MTech at Pondicherry University
B.E at North Maharashtra University
