Sahadev chaudhary

Software Engineer

West Delhi, Delhi, India8 yrs 9 mos experience
Highly Stable

Key Highlights

  • Senior lead CAD-DV engineer at Qualcomm
  • Expertise in VHDL and SystemVerilog
  • Strong background in Functional Verification
Stackforce AI infers this person is a VLSI and CAD engineering expert.

Contact

LinkedIn

Skills

Core Skills

VhdlSystemverilogFunctional Verification

Other Skills

LinuxBashShell ScriptingPerlMsieXpropProfilerXpessimismC (Programming Language)Mix language feature validationXceliumPerforceUniversal Verification Methodology (UVM)Cadence Virtuoso Layout EditorVerilog

Experience

8 yrs 9 mos
Total Experience
5 yrs 9 mos
Average Tenure
3 yrs
Current Experience

Qualcomm

Senior lead CAD-DV engineer

Jun 2023 – Present · 3 yrs · Noida, Uttar Pradesh, India · On-site

VHDLSystemVerilogLinuxBashShell ScriptingPerl+24

Cadence design systems

2 roles

Lead Product validation Engineer

Promoted

Jun 2022 – Jun 2023 · 1 yr

Product Validation Engineer II

Sep 2017 – Jun 2022 · 4 yrs 9 mos

Education

Gautam Buddha University

Master of Technology - MTech — VlSI

Jul 2015 – Jun 2017

Gautam Buddha University

Master's Degree — Electrical and Electronics Engineering

Jan 2015 – Jan 2017

ST. R.C. COLLEGE OF HIGHER EDUCATION SHAMLI ROAD, BANAT, MUZAFFARNAGAR

Stackforce found 100+ more professionals with Vhdl & Systemverilog

Explore similar profiles based on matching skills and experience

PS

Punyaslok swain

Senior R&D Engineer

at Synopsys Inc

India6 yrs 3 mos exp
Physical DesignStatic Timing AnalysisVerilogSystemVerilogTelemetry
TC

Tanmay Chakravorty

Senior Analog Design Engineer

at Synopsys Inc

Netherlands2 yrs 2 mos exp
Mixed-Signal IC DesignAnalog Circuit Design
AS

Ayesha Suhaila

Embedded System and IoT Intern

at CDAC Bangalore

Mangaluru, India0 mo exp
Embedded SystemsInternet of Things (IoT)VerilogApplication-Specific Integrated Circuits (ASIC)
SG

Sushant Kumar Gaurav

Senior R&D Engineer

at Synopsys Inc

Noida, India4 yrs 9 mos exp
Synopsys toolsVerification and Validation (V&V)
KR

KAVYA R

ASIC Digital Design Engineer Sr staff

at Synopsys Inc

Bengaluru, India9 yrs 6 mos exp
VerilogVerification and Validation (V&V)
RB

Rupam Banik

Sr Application Engineer

at Synopsys Inc

Gyeonggi, South Korea2 yrs 11 mos exp
Static Timing AnalysisVery-Large-Scale Integration (VLSI)DFTDigital IC Design
GP

Guru Kiran Pammi

Senior Principal Application Engineer

at Cadence Design Systems

Bengaluru, India18 yrs 6 mos exp
VLSIVery-Large-Scale Integration (VLSI)
VN

Vaibhavi Naik

Jr VLSI Engineer

at PRSsemicon Technologies (A PRSGroup company)

Bengaluru, India2 yrs 2 mos exp
VLSIEngineeringASIC DesignVerificationTeaching