N

Nitin Bhatt

Software Engineer

India2 yrs 11 mos experience

Key Highlights

  • Experienced in Universal Verification Methodology (UVM).
  • Strong foundation in SystemVerilog and Verilog.
  • Solid educational background in electronics from Delhi University.
Stackforce AI infers this person is a Digital Electronics Verification Engineer with expertise in UVM and SystemVerilog.

Contact

LinkedIn

Skills

Core Skills

Universal Verification Methodology (uvm)

Other Skills

SystemVerilogVerilogDigital ElectronicsMATLABSimulink

Experience

2 yrs 11 mos
Total Experience
--
Average Tenure
--
Current Experience

Synopsys inc

3 roles

R&D Engineering,Sr Engineer

Promoted

May 2026 – Present · 1 mo

R&D- 1 Engineer

Jul 2023 – May 2026 · 2 yrs 10 mos

Universal Verification Methodology (UVM)SystemVerilog

R&D trainee

Jul 2022 – Jul 2023 · 1 yr

Education

Delhi University

Master's degree — electronics

Jul 2020 – Jun 2022

Delhi University

Bsc electronic (hons) — electronics

Jan 2017 – Jan 2020

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