子育 邱 — Software Engineer
Senior Staff Engineer with over 7 years of experience in SRAM Compiler development and memory circuit design. Currently at Synopsys, I specialize in advanced node technologies, including Intel 18A, Samsung 4nm/8nm, and TSMC 5nm processes. My expertise lies in Design-Technology Co-Optimization (DTCO), developing test chips to meet customer requirements, and performing rigorous PPA (Power, Performance, Area) analysis and Read/Write Margin tuning. Previously at UMC, I gained a solid foundation in 40nm SRAM compiler development, verification flow establishment, and NVM (MRAM) test chip design. I am proficient in circuit characterization, silicon debugging, and yield enhancement. Technical Skills: Domain: SRAM Compiler, Memory Design, DTCO, PPA Analysis, Silicon Debug EDA Tools: HSPICE, HSIM, XA, Virtuoso, CustomSim, Solido, Nanotime Programming: Python, Perl, Shell Script
Stackforce AI infers this person is a Memory Design Engineer specializing in SRAM Compiler and advanced semiconductor technologies.
Location: Hsinchu County, Taiwan
Experience: 8 yrs 5 mos
Skills
- Sram Compiler
- Memory Design
Career Highlights
- Over 7 years in SRAM Compiler development.
- Expert in advanced node technologies.
- Proficient in PPA analysis and silicon debugging.
Work Experience
Synopsys Inc
Memory desgin Sr staff engineer (1 yr 4 mos)
Memory design Staff engineer (2 yrs)
Memory Designer (2 yrs 2 mos)
聯華電子股份有限公司
工程師 (2 yrs 11 mos)
Education
碩士 at National Tsing Hua University
