Aaditya Jain

Software Engineer

Bengaluru, Karnataka, India2 yrs 6 mos experience

Highly Stable

Key Highlights

3+ years in Analog/Mixed-Signal Layout Engineering
Expert in advanced physical verification techniques
Hands-on experience with TSMC and Intel process nodes

Stackforce AI infers this person is a Semiconductor Layout Engineer with expertise in Analog and Mixed-Signal design.

Contact

Skills

Core Skills

Analog Layout DesignPhysical Design

Other Skills

Analog LayoutDevice MatchingParasitic-aware LayoutEM/IR ReliabilityLatch-up PreventionAdvanced Physical VerificationFloor PlansPerl ScriptingUnix CommandsLayout DesignLDOShieldingStatic Timing AnalysisFloorplanningDigital Electronics

About

Analog / Mixed-Signal Layout Engineer with 3+ years of experience delivering production-quality layouts at advanced nodes (TSMC N2, N3, Intel 20A/18A). Currently working at Intel Corporation with end-to-end ownership of critical blocks such as Bandgap Reference (BGR) and LDO in Digital Thermal Sensor (DTS) IP. Strong expertise in device matching, symmetry, parasitic-aware layout, EM/IR reliability, latch-up prevention, antenna fixes, and advanced physical verification (DRC, LVS, ERC, HV, RV). Experienced in layout implementation of op-amps, current mirrors, differential pairs, comparators, level shifters, and power management circuits. Proficient with Cadence Virtuoso, IC Validator, STAR-RC, TOTEM, Riptide, Crossfire, along with Perl scripting and Linux-based design flows. Passionate about building robust, silicon-proven analog layouts and continuously improving circuit understanding.

Experience

2 yrs 6 mos

Total Experience

2 yrs 6 mos

Average Tenure

2 yrs 6 mos

Current Experience

Intel corporation

2 roles

Analog Layout Design Engineer

Nov 2023 – Present · 2 yrs 6 mos · Bengaluru, Karnataka, India

Analog LayoutDevice MatchingParasitic-aware LayoutEM/IR ReliabilityLatch-up PreventionAdvanced Physical Verification+2

Analog Layout Intern

Jun 2022 – May 2023 · 11 mos · Bengaluru, Karnataka, India

Internship in IPG PDE(Physical Design) team as analog layout Intern, hands-on
experience on emerging Intel’s process nodes and technology.
➢ Layout designing of all the standard cells and circuits like op amps, latches, current
mirrors and level shifters.
➢ Responsible for the layout design of LDO receiver and transmitter circuits, ensuring
compliance with design rules and standards
➢ Good exposure of matching, shielding, coupling, antenna layout challenges and analyzing/fixing EMIR issues.
➢ Skilled in using Perl scripting and good understanding of technology files and scripts.
➢ Parasitic RC extraction in layout designing on different test cases.
➢ Basic knowledge of Unix commands with experience using common commands for
file management