Ajay Sahoo — Product Manager
Low Power Methodology, UPF development & Static Low Power QC. Synthesis & Static Timing Analysis Domains. Hands on experience to Physical design flow(RTL to GDS flow). Hands on experience in custom layout design. Experience in Analog design in cadence virtuoso(ADC design).
Stackforce AI infers this person is a VLSI Design Engineer with expertise in low power methodologies and physical design.
Location: Bengaluru, Karnataka, India
Experience: 13 yrs 11 mos
Skills
- Low Power Methodology
- Static Timing Analysis
- Physical Design
- Custom Design
Career Highlights
- Expert in Low Power Methodology and Static Timing Analysis.
- Extensive experience in Physical Design flow from RTL to GDS.
- Proficient in custom layout design and Analog design.
Work Experience
Cadence
Senior Manager Product Engineering (1 yr 5 mos)
Product Engineering Manager (7 yrs)
Intel Corporation
SoC Engineer (1 yr)
MediaTek
Senior Engineer (3 yrs 3 mos)
IBM
Associate R&D Engineer (2 yrs 8 mos)
Education
mtech at Indian Institute of Technology, Kharagpur
