Ajinkya More

Product Engineer

Solapur, Maharashtra, India1 yr 3 mos experience

Key Highlights

Expert in physical design and ECO implementation.
Proven track record in advanced node technology.
Strong experience in low-power design techniques.

Stackforce AI infers this person is a Semiconductor and Embedded Systems specialist with strong physical design and digital electronics expertise.

Contact

Skills

Core Skills

Physical DesignEcoLow-power DesignDigital Electronics

Other Skills

FloorplanningPower PlanningPlacementCTSRoutingDRC & LVSAntenna Violation FixingECO ImplementationTiming ClosurePhysical VerificationPlace & RouteDRCCMOSI2C ProtocolFPGA

About

🔧 Hands-on Tools: Synopsys ICC2, PrimeTime . Open-source tools: OpenSTA, Magic, Yosys . 🧪 Technology Nodes Worked On: 40 nm. 📦 Block-Level Designs Handled: 1. 💻 Language : C , Verilog . 💻 Scripting Languages: Tcl, Perl. ⚙️ Physical Design Skills: • Floorplanning • Power Planning • Placement • CTS (Clock Tree Synthesis) • Routing • DRC & LVS • Antenna Violation Fixing • ECO Implementation • Timing Closure • Physical Verification

Experience

1 yr 3 mos

Total Experience

1 yr 3 mos

Average Tenure

Current Experience

Mediatek

Physical Design Engineer

Aug 2025 – Present · 9 mos · Bengaluru, Karnataka, India · On-site

Description : Tecnology Node : 6nm , Area : 1.83mm2 , Clock : , Power Domains : 5, Power Consumption : 104.89 mW, Supply Voltage 0.575V to 0.725V, Standard Cell Count : 4 Million, Macro Count : 111 .
I worked on a high-complexity 6nm PNR project (1.83 mm² core area) with ~4M standard cells and 111 macros across 5 power domains, operating at 0.575V–0.725V with total power of 104.89 mW.
The project involved significant floorplan and routing challenges. I iterated through 20+ floorplan versions to optimize macro placement and routing channels, reducing congestion hotspots from 1000+ to ~100 and eliminating 150+ shorts to zero, achieving clean routing.
Identified the root cause of unexpected buffer/inverter insertion caused by missing ignore pin constraints on 28 pins, which initially resulted in ~50K congestion violations. After applying proper constraints, achieved clean implementation and improved QoR.
Performed detailed timing analysis and identified combinational logic detours, applying appropriate false path constraints to improve timing convergence. During the ECO stage, fixed data transition and max capacitance violations to meet timing and signal integrity requirements.
Also resolved Base DRC and Metal DRC violations, ensuring clean physical verification and signoff readiness.
Through this project, gained strong exposure to floorplanning, congestion management, timing closure, ECO implementation, power integrity considerations, and full-chip signoff activities in advanced node technology.

FloorplanningPower PlanningPlacementCTSRoutingDRC & LVS+6

Rv skills design centre

Project Trainee

Nov 2024 – May 2025 · 6 mos · Banglore · On-site

Title : Block-Level ASIC Implementation of Agni Project Using Low-Power Techniques .
Description : Technology Node: 40nm , Area: 4.52 mm2 , Clock Frequency: 1 GHz , Number of
Power Domains: 9 , Number of Clock Domains: 4 , Power Consumption: 450mW , Maximum IR
Drop: 5% of Supply voltage , Supply Voltage: 1.18V to 1.1V , Number of Standard Cells: 0.4
million , Macro Count : 34.
Challenges :
Designing a floorplan that avoids narrow channels and routing congestion.
Creating a power plan that meets IR drop and Electromigration (EM).
Resolving DRC violations like Floating Wires, Metal Shorts, End of line pacing , Diff net via-cut pacing , Diff net spacing , Less then minimum area , overlap of Vias and Macro pin shorts.
Analysing and Resolving Max transition violations caused by ineffective buffering.
Resolving the congestion after placement.
Analysing the timing reports to understand and resolve the setup and hold violations .
Handling redundant level shifter insertion, unassociated level shifters, and missing isolation cell insertion at domain boundaries.
Ran into LVS errors, antenna violations, and metal shorts, resolved by inserting antenna diodes, using metal jumpers, and manually correcting shorts.

Place & RouteDigital ElectronicsPhysical DesignLow-power Design

Vidyaleap

VLSI INTERN

Jan 2024 – Jun 2024 · 5 mos · Pune District, Maharashtra, India · On-site

Title : Inplementation of I2C Master on Artix-7 Basys3 FPGA and Interfacing with MPU9250 .
Description :
Full Functional Single I2C Master as per I2C Protocol Standard.
7-bit device address and 400KHz data rate.
Capability for interrupt generation for Data exchange and Error reporting.
Integration of the developed I2C Master with MPU9250, a 9-axis sensor, ensuring seamless data exchange and communication.

CMOSDigital Electronics