Amit Dudeja

Product Manager

Hyderabad, Telangana, India16 yrs 7 mos experience

Most Likely To SwitchAI ML Practitioner

Key Highlights

17 years of experience in Semiconductor and EDA industries.
Expert in System Level Design and Performance Modeling.
Proven leadership in building and managing engineering teams.

Stackforce AI infers this person is a Semiconductor and EDA expert with strong leadership in performance modeling.

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Skills

Core Skills

System Level DesignPerformance ModelingPower EstimationIp ModelingSoftware Development

Other Skills

SystemCSimulation FlowMemory ControllersPCIe ControllerInterconnectNOCUVM RTL CorrelationAI AlgorithmsPerformance AnalysisTLM2.0Traffic Generator IP ModelRTL SimulationUPF3.0TclPython

About

Around 17 years of rich experience in Semiconductor, EDA and Software industries, majorly in the domain of System Level (ESL) design, development and verification. Having experience of performance and power modeling for architecture exploration use case using SystemC and TLM2.0. Also worked on AI workload modelling for architectural exploration. Built and leading the team of engineers working on SystemC simulation flows of AMD FPGA. System Standard: SystemC/TLM2.0 Programming Languages : C, C++, Data Structures & Algorithms Hardware Description Languages: Verilog, VHDL, SystemVerilog Verification Methodology: UVM Scripting Language: Tcl, Perl IEEE Power Standard: UPF3.0 Bus Protocols: HBM,DDR,LPDDR,AXI , Tensilica PIF Protocol Tools: Synopsys PA tools for architecture exploration (PA-MCO & PA-Ultra), TLMC,Xilinx Vivado

Experience

16 yrs 7 mos

Total Experience

2 yrs 9 mos

Average Tenure

4 yrs 4 mos

Current Experience

Amd

2 roles

SMTS Design Engineer/Manager

Promoted

Jul 2024 – Present · 1 yr 10 mos · Hyderabad, Telangana, India

Built and Leading the team of 15 engineers
Working on enabling SystemC simulation flow of AMD FPGA
Performance Modelling of memory controllers, pcie controller and interconnect

SystemCSimulation FlowPerformance ModelingMemory ControllersPCIe ControllerInterconnect+1

MTS Design Engineer/Manager

Dec 2021 – Jun 2024 · 2 yrs 6 mos · Hyderabad, Telangana, India

Started SystemC modelling team from scratch
Managing team of very talented engineers
Project lead for performance models of NOC and memory controllers
Performance modelling of latest memory controllers and NOC
UVM RTL correlation of performance models

SystemCPerformance ModelingNOCMemory ControllersUVM RTL CorrelationSystem Level Design

Synopsys inc

3 roles

Senior Research And Development Engineer 2

Jun 2018 – Dec 2021 · 3 yrs 6 mos

a. Developed a framework for creating the performance model of AI algorithms used for early architecture exploration
b. Developed a hybrid solution used for performance analysis of RTL simulation in Synopsys Platform Architect Tool chain
c. Developed a system level traffic generator IP model used for generating different traffic patterns for architectural exploration.
d. Developed different SystemC/TLM2.0 based models for Customer projects.
e. Responsible for Tensilica transactors, Generic Memory and other SytstemC IPs used for performance modeling.
f. Developed multi ported multi banked SystemC/TLM2 SRAM model from scratch to be used for performance exploration in AI use case
h. Lead the team of engineers

AI AlgorithmsPerformance AnalysisSystemCTLM2.0Traffic Generator IP ModelPerformance Modeling+1

Senior Research And Development Engineer

Promoted

Jul 2014 – Jun 2018 · 3 yrs 11 mos

a. Created SystemC transactors for importing Tensilica IPs in the Synopsys PA tools.
b. Worked on supporting IEEE 1801 -2015 aka UPF3.0 for Power estimation at System level in Synopsys Tool chain
c.Developed and Own a hybrid solution used for performance analysis of RTL simulation in Synopsys Platform Architect Tool chain
d. Own a system level traffic generator IP model used generating traffic captured in RTL

SystemCUPF3.0Performance AnalysisTraffic Generator IP ModelPower EstimationSystem Level Design