Ashutosh Singh — Software Engineer

I am currently working as SoC Physical Design Engineer in Full chip layout Team (FCL). I have learned basic FCL flow and the technology specific integration constraints/rules. I have developed basic understanding of the floorplan, diefile and RDL feasibility closure meeting all TR criteria for die-size, LFU, channel estimation, routability & PKG study. I have worked on the FCL for the IPU & display SS under an FCL lead. The task involves multiple FCL churns as per SOC level floorplan changes, continuous interactions with multiple stakeholders across sites and maintaining the most optimized area for the IPs meeting all PDN requirements.

Stackforce AI infers this person is a Physical Design Engineer with expertise in Engineering Procurement and Construction.

Location: Roorkee, Uttarakhand, India

Experience: 5 yrs 1 mo