Bandana Prasad — Software Engineer
Physical Design Engineer competent in Timing Closure and Constraints Development with around 6 years of experience in the Semiconductor Industry. - Worked on every aspect of Timing Domain, From RTL Feedback to Design ECO's. - Efficiently handled multiple block-level static-timing analysis. - Well versed with Liberty timing models. - Involved in timing closure of IO Interfaces like ENET, DSPI, JTAG etc. - Hands-on timing tools: Primetime and Tempus. - Languages - Tcl | csh | Perl
Stackforce AI infers this person is a Semiconductor Engineer specializing in Timing Closure and Static Timing Analysis.
Location: Bengaluru, Karnataka, India
Experience: 8 yrs 5 mos
Skills
- Static Timing Analysis
- Timing Ecos
- Constraints
Career Highlights
- Expert in Static Timing Analysis and Timing Closure.
- Proficient in multiple timing tools including PrimeTime and Tempus.
- Strong background in Semiconductor industry with 6 years of experience.
Work Experience
Silicon Engineer (1 yr 8 mos)
Qualcomm
Sr. Timing Signoff Engineer (2 yrs 2 mos)
NXP Semiconductors
Senior Design Engineer (3 mos)
Design Engineer (1 yr 8 mos)
Intern - STA, Physical Design Engineer (11 mos)
Indraprastha Institute of Information Technology, Delhi
Teaching Assistant (11 mos)
Internshala
Training Course (1 mo)
IEEE
WIE Vice Chairperson, USICT Student Branch (1 yr 1 mo)
Steel Authority of India Limited
Industrial Trainee (1 mo)
Education
Master of Technology - MTech at Indraprastha Institute of Information Technology, Delhi
USICT at Guru Gobind Singh Indraprastha University
