Sep 2016 – Jul 2023 · 6 yrs 10 mos · Hyderabad Area, India

Jan 2013 – Aug 2016 · 3 yrs 7 mos · Hyderabad Area, India · On-site

• worked on custom memory layout's on 28nm tech.
• Presently working on 16FFp technology.

Jan 2012 – Jun 2012 · 5 mos · Noida

• Work Done:
• 1. Verification Of SAR ADC, Bandgap Refeence Circuit, Power On Reset
• Circuit, Low Dropout Regulator using Eldo simulator(Mentor Graphics).
• 2. Modeling of SAR ADC, Power Management Unit in Behavoural Model
• using Verilog HDL and verified using NCsim simulator(Cadence).
• Projects:
• Title: Implementation of High Speed and Low Power Encoder for Flash ADC Brief Overview: A new high speed and low power encoder architechture for thermometer to binary code conversion in flash ADC's is proposed and implemented in static CMOS 180nm technology. The results have been compared with other flash encoders
• Title: Implementation of parallel Prefix Adders using Verilog HDL
• Brief Overview: Implemented several parallel prefix adders using Verilog HDL. Adders are Simulated and Synthesized in Verilog & NC Verilog.
• Title: Designed and Implementation of 4-Bit parallel ALU
• Brief Overview: Implemented A 4-Bit ALU which can be performed both Arithmetic and Logical operation.
• Title: Schematic, Layout and Simulation of various Full Adder Circuits
• Brief Overview: Implemented Various Full Adder Circuits using CMOS, Transmission Gates and Pass Transistor.
• Title: Maximum Video Compression using AC Prediction Algorithm
• Brief Overview: Image is compressed using DCT Algorithm and Reconstructed using AC Coefficients based on the knowledge of image Compression. Video is compressed using DCT algorithm then Reconstructed using DCT Algorithm and then reconstructed using AC Coefficients.

Jun 2009 – May 2010 · 11 mos

• Subjects dealt Digital Design, Electronic Devices and Circuits, VLSI Design, Linear Integrated Circuits.