Deepak Nagaria

CEO

Delhi, Delhi, India12 yrs 10 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Expert in IP Verification with extensive R&D experience.
  • Proficient in advanced memory technologies and UCIe standards.
  • Strong background in VLSI design and functional verification.
Stackforce AI infers this person is a specialist in semiconductor design and verification, focusing on advanced memory technologies.

Contact

LinkedIn

Skills

Core Skills

Ip Verification

Other Skills

UCIe 3.0 AdapterFDIRDIUCIe 2.0Manageability over UCIeMPGMTPUMAPAXI over UCIeUCIe AdapterDDR5 RDIMMMRDIMMLPDDR5DDR5 NVDIMM-PRDIMM

Experience

12 yrs 10 mos
Total Experience
6 yrs 5 mos
Average Tenure
10 yrs 3 mos
Current Experience

Synopsys inc

7 roles

R&D Principal

Promoted

May 2026 – Present · 1 mo

  • UCIe 3.0 Adapter, FDI, RDI
UCIe 3.0 AdapterFDIRDIIP Verification

R&D Sr. Staff

Promoted

Mar 2024 – Apr 2026 · 2 yrs 1 mo

  • UCIe 2.0, Mangeability over UCIe, MPG, MTP, UMAP, AXI over UCIe
UCIe 2.0Manageability over UCIeMPGMTPUMAPAXI over UCIe+1

R&D Staff

Jul 2023 – Feb 2024 · 7 mos

  • UCIe Adapter, RDI, FDI
UCIe AdapterRDIFDIIP Verification

Sr. R&D Engineer II

Jul 2021 – Jun 2023 · 1 yr 11 mos

  • DDR5 RDIMM, MRDIMM
  • UCIe Adapter, RDI
DDR5 RDIMMMRDIMMUCIe AdapterRDIIP Verification

Sr. R&D Engineer I

Promoted

Jan 2019 – Jun 2021 · 2 yrs 5 mos

  • LPDDR5
  • DDR5 NVDIMM-P, RDIMM
LPDDR5DDR5 NVDIMM-PRDIMMIP Verification

R&D Engineer II

Jan 2017 – Dec 2018 · 1 yr 11 mos

  • LPDDR4, 4X
  • LPDDR5
LPDDR44XLPDDR5

R&D Engineer I

Sep 2015 – Dec 2016 · 1 yr 3 mos

  • JEDEC eMMC, SD, UHSII
JEDEC eMMCSDUHSII

Arrow devices

Design and Verification Engineer

Feb 2013 – Sep 2015 · 2 yrs 7 mos · Bengaluru Area, India

  • MIPI M-PHY 2.0, 3.0 and 3.1
  • USB 3.0, 3.1 PHY
  • USB-PD 2.0 PHY
MIPI M-PHY 2.03.0 and 3.1USB 3.03.1 PHYUSB-PD 2.0 PHY

Education

CDAC

PG Diploma — VLSI Design

Jan 2012 – Jan 2013

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