Dikshya Panda — Software Engineer
• Good exposure of Signoff STA & Timing ECO flow at SoC Modem (4G/5G) integration level. • Experience in Synthesis, Pre-STA and Pre-layout netlist quality checks of bus logic/Modem blocks in SoC. • Involved in RTL Quality Lint checks of SoC subsystems. • Good knowledge and experience in Low power design check at Modem integration level.
Stackforce AI infers this person is a specialist in semiconductor design and verification for 4G/5G technologies.
Location: Bengaluru, Karnataka, India
Experience: 8 yrs 5 mos
Skills
- Signoff Sta
- Timing Eco Flow
Career Highlights
- Expert in Signoff STA and Timing ECO for SoC integration.
- Proficient in low power design checks at Modem integration level.
- Experienced in RTL Quality Lint checks for SoC subsystems.
Work Experience
Cadence Design Systems
Lead Design Engineer (4 yrs 4 mos)
MediaTek
Senior Design Engineer (2 yrs 6 mos)
Design Engineer (11 mos)
Student Intern (6 mos)
Accenture
Associate Software Engineer (8 mos)
Education
Master of Technology - MTech at International Institute of Information Technology Bangalore
Bachelor of Technology - BTech at GITAM Deemed University
