Gopal Ledange

Software Engineer

Bengaluru, Karnataka, India12 yrs 6 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Expert in RTL to GDS flow across multiple technologies.
  • Proficient in physical design and verification methodologies.
  • Strong background in digital IC design and device modeling.
Stackforce AI infers this person is a VLSI Design Engineer with expertise in physical design and digital electronics.

Contact

LinkedIn

Skills

Core Skills

Physical DesignStatic Timing AnalysisDigital Ic DesignDevice Modeling

Other Skills

Clock Tree SynthesisLogic SynthesisRC ExtractionVHDLVerilogXilinxModelsimngspiceCVLSIMatlabCadence VirtuosoXilinx ISEC++FPGA

About

Working as a Physical Design Engineer , Having hands-on experience in: * Complete RTL to GDS flow at 5ns,14nm, 28nm, * Synthesis, Static timing analysis, Floor Planning, Power Planning and Placement * Clock tree synthesis, Routing,and Parasitic Extraction.DFT using RC-compiler, ILM flow * Physical verification * Experience in various technologies - 14nm, 28nm * Knowledge on static IR-drop, cross talk and electro-migration analysis, and OCV and AOCV * Expertise in TCL and shell scripts

Experience

12 yrs 6 mos
Total Experience
3 yrs 1 mo
Average Tenure
8 yrs 3 mos
Current Experience

Intel corporation

Physical Design Engineer

Feb 2018 – Present · 8 yrs 3 mos · Bengaluru Area, India

Physical DesignClock Tree SynthesisStatic Timing AnalysisLogic SynthesisRC Extraction

Wafer space

Design Engineer-1

Mar 2017 – Feb 2018 · 11 mos · bangalore

Dxcorr design inc

Physical Design Engineer

Oct 2015 – Mar 2017 · 1 yr 5 mos · Bengaluru Area, India

Nit nagpur

Graduate Teaching Assistant

Jul 2013 – Jun 2015 · 1 yr 11 mos · India

  • I asisted professors in conducting Digital IC Design and Device modeling labs. For Digital IC Design lab we used VHDL, Verilog, Xilinx and Modelsim tools and for Device simulation lab we used ngspice tool for extracting the Device Parameters and simulating the circuits.
VHDLVerilogXilinxModelsimngspiceDigital IC Design+1

Education

Visvesvaraya National Institute of Technology

Master’s Degree — VLSI

Jan 2013 – Jan 2015

SVPM COE Malegaon BK

Bachelor’s Degree — Electronic and Telecommunication

Jan 2008 – Jan 2012

Mahtmaphule College Ahamadpur

HSC (XII)

Jan 2006 – Jan 2007

Yeshwant Vidyalaya, Ahamadpur Dist-Latur

SSC (X)

Jan 2004 – Jan 2005

Stackforce found 100+ more professionals with Physical Design & Static Timing Analysis

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