Goutami A

Software Engineer

Bengaluru, Karnataka, India18 yrs 2 mos experience

Highly Stable

Key Highlights

Expert in Physical Design Verification and Flow Automation.
Proficient in Calibre and Virtuoso tools for semiconductor design.
Extensive experience in leading verification flow development.

Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in Physical Design Verification.

Contact

Skills

Core Skills

Physical Design VerificationFlow Automation

Other Skills

CalibreVirtuosoDebuggingRule DecksRegression SuitesPhysical VerificationTCLLVSDRCC++DFMCSolarisUnixProgramming Languages

About

Experienced in Chip integration and tapeout, Physical Design Verification and Flow development Physical design Verification Tools: ICV, Calibre P&R and Design Tools: Fusion Compiler, Innovus, Virtuoso Design Framework, Programming Languages: Perl, Tcl, C++/C, HTML Hardware Languages: SKILL, SPICE

Experience

18 yrs 2 mos

Total Experience

4 yrs 1 mo

Average Tenure

1 yr 7 mos

Current Experience

Nvidia

Principal Engineer

Oct 2024 – Present · 1 yr 7 mos · Bengaluru, Karnataka, India

Intel corporation

SoC Design Engineer

Nov 2019 – Oct 2024 · 4 yrs 11 mos · Bengaluru, Karnataka, India

Apple

Physical Design Verification Engineer

Apr 2017 – Aug 2019 · 2 yrs 4 mos · Cupertino, California

Oracle

2 roles

Principal Hardware Engineer

Promoted

Nov 2013 – Mar 2017 · 3 yrs 4 mos

Technology Nodes: 20nm, 10nm, 7nm
Physical Design Verification Flow Automation
DRC-type/LVS/DFM Calibre Rule deck generation for verification and analysis (SVRF/TVF)
Calibre/Virtuoso Tool Usage, Debug. (Includes Calibre DRV, Cadence SKILL scripting)
PV Tool evaluation

Physical Design VerificationFlow AutomationCalibreVirtuosoDebugging

Senior Hardware Engineer

Feb 2010 – Nov 2013 · 3 yrs 9 mos

Technology Nodes: 40nm, 32nm, 28nm, 20nm.
Lead developer for Physical Design Verification flow ; Tool evaluation ; Support Calibre Rule Decks.

Physical Design VerificationCalibreRule Decks

Sun microsystems

Member of Technical Staff

Nov 2007 – Feb 2010 · 2 yrs 3 mos · Santa Clara, CA

Technology Nodes: 45nm,40nm, 32nm
Developer for Physical Design Verification flow ; Develop Regression Suites ; Support Calibre Rule Decks.

Physical Design VerificationCalibreRegression Suites

Education

University of Southern California

Masters — VLSI

Jan 2005 – Jan 2007

Jawaharlal Nehru Technological University

BTech — ELectronics and Communications

Jan 2001 – Jan 2005

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