Jyoti Yadav

Software Engineer

Bengaluru, Karnataka, India10 yrs 6 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Expert in functional verification and UVM testbench development.
Proven track record in debugging complex hardware designs.
Strong background in multi-core processor communication protocols.

Stackforce AI infers this person is a Hardware Verification Engineer with expertise in multi-core processor architectures.

Contact

Skills

Core Skills

Functional VerificationUvmDebugging

Other Skills

SystemVerilogTestbench DevelopmentPERL ScriptingC++CVHDLMicrosoft OfficeMatlabPowerPointMicrosoft ExcelMicrosoft WordVerilogProgrammingData StructuresJava

About

Design verification engineer

Experience

10 yrs 6 mos

Total Experience

5 yrs 3 mos

Average Tenure

8 yrs 6 mos

Current Experience

Qualcomm

3 roles

Staff Engineer

Promoted

Dec 2023 – Present · 2 yrs 5 mos

Sr. lead engineer

Dec 2020 – Nov 2023 · 2 yrs 11 mos

Senior Engineer

Oct 2017 – Nov 2020 · 3 yrs 1 mo

Oracle india pvt. ltd

2 roles

Hardware Developer

Dec 2016 – Aug 2017 · 8 mos

Project: Functional verification of “Coherency link crossbar ”. It is used for inter-node and IO communications in next gen SPARC processors.
Developed UVM based Testbench, which includes various components like driver, monitor,
scoreboard, sequencer etc.
Generated random and directed stimulus.
From design specification, implemented bench checkers using SystemVerilog Assertions.
Owns functional coverage of “Coherency link crossbar ” at block level verification, and drove functional coverage and code coverage to closure.
Developed irritators for design, for creating complex test cases for block level verification.
Debugged complex regression failures and discovered bugs in design.

UVMSystemVerilogFunctional VerificationTestbench DevelopmentDebugging

Associate Hardware Developer

Jul 2015 – Nov 2016 · 1 yr 4 mos

Project: Functional verification of “Rail". “Rail” is an important communication link in multi-core environment, channels communication between L2, L3 Caches, Coherency ordering unit & database accelerator.
Drove functional coverage of "Rail" towards closure.
Owns interface functional coverage of “L3 cache”. Learnt coherency protocol for multi-core processors.
Developed irritators for "Rail", created complex test cases employing irritators, discovered corner case bugs in design.
Created PERL scripts for diagnostic log's post processing, employed it for debugging regression failures.
Debugged various regression failures and filed design bugs.

Functional VerificationPERL ScriptingDebugging