MANGESH KONDALKAR — Software Engineer

Design Verification Lead | UVM | System-Verilog | Formal Verification | VLSI Expert | Author Gold Medalist in Electronics Engineering (B.Tech, Mumbai University) and M.Tech in VLSI Design with Distinction (VTU). I bring 11+ years of experience in Design Verification domain with expertise in UVM, System-Verilog, and Advanced Verification Methodologies. Experience in developing complex testbench for IP and Subsystem verification, ensuring robust and high-quality designs. Currently, I lead a team of 5+ DV engineers for an IP used in AI/ML hardware. My responsibilities include planning effort estimates, Testbench strategy to verify new IP features and delivering bug free RTL across multiple projects. Hands on experience in Formal verification tools (JG & VCF) and methodologies like FPV & SEQ. Proven track record in driving Innovation and Quality in DV methodologies. Published papers in internal and external DV forums (DVCon & DTDC).

Stackforce AI infers this person is a VLSI and Formal Verification expert in the Semiconductor industry.

Location: Bengaluru, Karnataka, India

Experience: 12 yrs 9 mos