Meher Kiran Rajamahanti

Product Engineer

Srikakulam, Andhra Pradesh, India2 yrs 2 mos experience
Most Likely To Switch

Key Highlights

  • Hands-on experience in VLSI design and verification.
  • Proficient in multiple programming and scripting languages.
  • Strong foundation in digital logic and semiconductor technologies.
Stackforce AI infers this person is a VLSI Design Engineer with expertise in semiconductor technologies and digital design.

Contact

LinkedIn

Skills

Core Skills

VerilogSystemverilogVlsi DesignRtl Design

Other Skills

TCLPerlRTL CodingXilinx ISELogic DesignAssembly LanguageProcessor ArchitectureCPPCLinuxAXI4PMOSNMOSInverter DesignDynamic Circuits Design

Experience

2 yrs 2 mos
Total Experience
1 yr 4 mos
Average Tenure
2 yrs 1 mo
Current Experience

Soctronics

2 roles

Engineer1

Apr 2025 – Present · 1 yr 2 mos

  • Working in Design For Debug (DFD)

Engineer Trainee

Apr 2024 – Mar 2025 · 11 mos

Amd

Design Verification Engineer (Contract)

May 2024 – Present · 2 yrs 1 mo · Hyderabad, Telangana, India · On-site

Veda iit

VLSI Design Trainee

Jul 2023 – Mar 2024 · 8 mos · Guntur, Andhra Pradesh, India · On-site

TCLPerl

Tech mahindra cerium pvt ltd

VLSI Trainee Support

Nov 2022 – Mar 2023 · 4 mos · Bengaluru, Karnataka, India · Remote

  • Successfully completed internship titled "VLSI Design Foundation" where I got industrial exposure with hands on experience on Verilog, System Verilog, UVM and Logic Design. I had done projects titled Design of Traffic Light Controller, FIFO (Synchronous & Asynchronous), Sequence detectors, Elevator and assignments and all these projects are done using Verilog for design codes and System Verilog for testbenches.
RTL CodingXilinx ISEVerilogSystemVerilog

Education

GMR Institute of Technology (GMRIT), GMR Nagar, Rajam, Srikakulam Dt.,-532127 (CC-34))

Bachelor of Technology - BTech — Electronics and Communications Engineering

Aug 2019 – Apr 2023

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