Mitesh Kalal

Software Engineer

Bengaluru, Karnataka, India4 yrs 8 mos experience

Highly Stable

Key Highlights

4.5+ years in design verification engineering.
Expert in UVM and high-speed memory protocols.
Achieved >95% code coverage in GDDR7 IP verification.

Stackforce AI infers this person is a Semiconductor Verification Engineer with expertise in memory subsystem and design verification.

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Skills

Core Skills

Universal Verification Methodology (uvm)Functional VerificationRtl VerificationEmbedded Systems

Other Skills

LPDDR5-based Memory Subsystem VerificationUVM-based testbench componentstest planscoverage modelsUVMUVM-based VIP Integrationsimulation performancecode coverageroot-cause analysisSystemVerilogVerilogJTAGCDC analysislinting toolsPhysics

About

Verification Engineer with 4.5+ years of experience in the industry specializing in LPDDR based MEMSS Verification(Membridge),GDDR7 IP verification, and a year-long internship in RTL. Proficient in UVM-based environments, highspeed memory protocols, and ensuring first-pass silicon success. Skilled in debugging, test plan development, and optimizing verification processes for performance-critical designs.

Experience

4 yrs 8 mos

Total Experience

4 yrs 8 mos

Average Tenure

4 yrs 8 mos

Current Experience

Intel corporation

3 roles

GPU Design Verification Engineer

Mar 2025 – Present · 1 yr 2 mos · Bengaluru, Karnataka, India · On-site

Working on LPDDR5-based Memory Subsystem Verification, focusing on
MEMBRIDGE (Protocol conversion).
Developing UVM-based testbench components to validate protocol
conversion and ensure data integrity across interfaces.
Creating test plans and coverage models for memory bridge scenarios
including corner cases, protocol violations, and performance stress
testing.

LPDDR5-based Memory Subsystem VerificationUVM-based testbench componentstest planscoverage modelsUniversal Verification Methodology (UVM)Functional Verification

IP Design Verification Engineer

Aug 2021 – Feb 2025 · 3 yrs 6 mos · Bengaluru, Karnataka, India · On-site

UVM-based VIP(BFM) Integration and verification of key features for GDDR7 IP.
Developed test plans and implemented constrained-random, directed, and corner-case test scenarios.
Enhanced simulation performance by optimizing testbench components and using assertions for early bug detection.
Achieved >95% Code coverage and 100% functional coverage, ensuring the IP met stringent quality standards.
Performed root-cause analysis for calibrations, Loopbacks, Eye trainings
Supported Post-Si and SoC teams for Debugs
Collaborated with RTL, Firmware and modeling teams to resolve design bugs.

UVM-based VIP Integrationtest planssimulation performancecode coverageroot-cause analysisUniversal Verification Methodology (UVM)+1

SOC Design Intern

Aug 2020 – May 2021 · 9 mos · Bengaluru, Karnataka, India

Understanding System Verilog along with Verilog.
Given presentation to the team on various System Verilog topics.
Understanding the design (Coding Style) of the implemented project.
Documentation on initial steps to be followed at Intel to start with any project.
Study on JTAG (Joint Test Action Group) interface implementation for debug and testing purposes at Intel.
Conducted Clock Domain Crossing (CDC) analysis using industry standard tool (Spyglass) to identify and mitigate potential synchronization issues.
Utilized linting tools (SpyGlass) to perform design rule checking, detect coding issues, and enforce coding guidelines.
Implementation of DFx features (Viewtree and VISA) in the Design.

System VerilogVerilogJTAGCDC analysislinting tools

Gyanjyot institute

Tutor

Jun 2017 – Jun 2019 · 2 yrs · Ahmedabad, Gujarat, India

Physics and Mathematics tutoring for Class 11 and 12 Science stream [ English and Gujarati Medium].
Helped students solving doubts and clearing the concepts for academics and competitive exams [JEE and NEET].

PhysicsMathematics

Institute for plasma research

Engineer Intern

Dec 2016 – Mar 2017 · 3 mos · Gandhinagar, Gujarat

Aim: Development of PXI based data acquisition system synchronized with timing module using LABView.
Developed and configured a PXIe based hardware setup.
The system can be used for continuous data acquisition with timestamp for steady state experiments.
Developed a GUI using graphical programming in LabVIEW that can be used to set the required sampling rate and other configurations like trigger, number of samples to be captured and to display the acquired data.
Interfaced the system with GPS module.
Thus 2 or more devices in different time zones can be configured to acquire data using GPS time reference, which makes it easy to compare data of events from across the globe [for eg. Gravitational wave detection].

PXIdata acquisitionLabVIEW