Mohammed Anam Rashid

Product Engineer

Bengaluru, Karnataka, India0 mo experience

Key Highlights

Proficient in UVM and SystemVerilog for design verification.
Hands-on experience with leading EDA tools.
Strong foundation in VLSI design and verification methodologies.

Stackforce AI infers this person is a VLSI Design Verification Engineer with expertise in advanced verification methodologies.

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Skills

Core Skills

Design VerificationVerification Methodologies

Other Skills

SystemVerilogUniversal Verification Methodology (UVM)VerilogConstraint Random Coverage Driven VerificationSVAUVMSynopsys -VCSQuestaSimXlinixLinuxPerlSVInterfacesAssertionsProgramming

About

I am a dedicated Design and Verification Engineer with a strong focus on Design and Verification. I have hands-on experience with a wide range of EDA tools and am proficient in Universal Verification Methodology (UVM). My goal is to ensure that every design I work on is efficient, reliable, and meets the highest industry standards. My VLSI domain skills include, - HDL: Verilog - HVL: System Verilog - Verification Methodologies: Constraint Random Coverage Driven Verification - Assertion-Based Verification: SVA - TB Methodology: UVM - Tool: Synopsys -VCS, Mentor Graphics –QuestaSim, Xlinix - Domain: ASIC/FPGA front-end Design and Verification - Operating System: Linux - Scripting Languages: Perl I am currently seeking new opportunities in the design and verification field where I can apply my skills and continue to grow. Let's connect if you're looking for someone who is committed, skilled, and ready to contribute to your team's success.

Experience

0 mo

Total Experience

Average Tenure

Current Experience

Mediatek

Design Verification Engineer

Jul 2025 – Present · 10 mos · Bengaluru, Karnataka, India · On-site

SystemVerilogUniversal Verification Methodology (UVM)Design VerificationVerification Methodologies

Maven silicon

2 roles

Design Verification Engineer- Intern

Aug 2024 – Jul 2025 · 11 mos · On-site

SystemVerilogUniversal Verification Methodology (UVM)

Design and Verification

Oct 2023 – Present · 2 yrs 7 mos · On-site

Worked on VLSI domains as listed below,
HDL: Verilog
HVL: System Verilog
Verification Methodologies: Constraint Random Coverage Driven Verification
Assertion Based Verification: SVA
TB Methodology: UVM
Tool: Synopsys -VCS, Mentor Graphics –QuestaSim, Xlinix
Domain: ASIC/FPGA front-end Design and Verification
Operating System: Linux
Scripting Languages: Perl
Core Skills: RTL Coding using Synthesizable constructs of Verilog,
FSM based design, Simulation, CMOS Fundamentals, Code Coverage, Functional Code
Coverage, Synthesis, Static Timing Analysis Assertion Based Verification.
Worked on various projects,
Mod12 Loadable Up-Down Counter: Implemented RTL using Verilog HDL || Architected Class based verification using SystemVerilog || Verified RTL in SystemVerilog || Generated functional and Code Coverage for the RTL verification sign-off.
Router 1X3: Architected the block-level structure for the design || Implemented RTL Using Verilog HDL || Architected the Class based Verification environment in UVM || Verified the RTL model using UVM || Generated functional and Code Coverage for the RTL verification sign-off.
AHB2APB Bridge: Architected the block-level structure for the design || Implemented RTL Using Verilog HDL || Architected the Class based Verification environment in UVM || Verified the RTL model using UVM || Generated functional and Code Coverage for the RTL verification sign-off.