NIKHIL KULKARNI

Software Engineer

Bengaluru, Karnataka, India10 yrs 7 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Expert in SoC Physical Design across advanced technology nodes.
Proven track record of successful production tape-outs.
Strong expertise in PPA optimization and timing closure.

Stackforce AI infers this person is a Semiconductor Design Engineer with extensive experience in Physical Design and SoC methodologies.

Contact

Skills

Core Skills

Physical DesignSoc DesignApplication Engineering

Other Skills

SynthesisFloor planningClock Tree synthesisTiming AnalysisECO tasksICC-II tool40nm technology7nm technologyPartition ExecutionECO implementationStatic Timing AnalysisVerilogVLSICLinux

About

• Extensive experience in SoC Physical Design implementation across advanced technology nodes (40nm to 3nm), handling complex, congested, and high-frequency blocks (500 MHz–2 GHz) with instance counts ranging from 300K to 2M and utilization up to 73%. • End-to-end ownership of RTL-to-GDSII flow including synthesis, floorplanning, CTS, placement, routing, timing/SI closure, ECOs (timing & functional), and multi-voltage design support. • Strong expertise in PPA optimization through CTS tuning, library analytics, congestion reduction, sequential clustering, clock gating, dynamic power optimization (SAIF), and advanced experimentation methodologies. • Proven track record of multiple production tape-outs, block ownership, partition convergence, ECO execution, and final sign-off using industry-standard PD tools and flows.

Experience

10 yrs 7 mos

Total Experience

2 yrs 7 mos

Average Tenure

2 yrs 10 mos

Current Experience

Qualcomm

Staff Engineer

Jul 2023 – Present · 2 yrs 10 mos · Bengaluru, Karnataka, India · On-site

Intel corporation

2 roles

SoC Design Engineer

Sep 2019 – Jun 2023 · 3 yrs 9 mos · Bengaluru, Karnataka, India · Hybrid

Physical Design Implementations for various design decisions, SOC Design
methodology, flow, and implementation for better optimized design in 14nm, 10nm,
7nm, 3nm and Intel lower technology nodes, executed on congested and timing complex
blocks with clock frequency between 500 MHz - 2 GHz, total cell count from 300k to 2M,
Utilization with 45-70%.
Implement and Support blocks with multi-voltage designs for all aspects of Physical
Design flows covering Synthesis, Floor planning, Clock Tree planning & analysis,
Placement, Clock tree synthesis, Placement optimizations, Routing, Timing and SI
analysis/closure, ECO tasks (both timing and functional) analysis & fixes
Three production Tape-out with significant contribution to complete RTL 2 GDSII tasks
including its derivatives and managed more than 15 blocks.

Physical DesignSynthesisFloor planningClock Tree synthesisTiming AnalysisECO tasks+1

Graphics Hardware Engineer

Sep 2015 – Apr 2019 · 3 yrs 7 mos · Bengaluru Area, India · On-site

Have worked as Partition Execution Owner (PEO) in converging partitions for timing,
routing, and other aspects and have particularly good hands-on experience PNR flow.
Worked as SPVO (Section PV owner) where I provided solutions for external timing
fixes.
Worked on a 10nm project with 1.8 M instance count with 73% utilization.
Successfully tape-in ~5 functional blocks.
Hands-on experience in various stages of Physical Design flow such as Synthesis,
Floorplan, Placement, Congestion analysis and reduction, Timing Analysis and Fixes,
Clock Tree Synthesis, Routing, Static Timing Analysis, ECO implementation and Final
PDV sign-off.
Good hands-on experience on ECO techniques and last mile convergence techniques.
Used Synopsys Lynx design system (RTM) for PNR flow.

Partition ExecutionTiming AnalysisECO implementationStatic Timing AnalysisPhysical Design

Synopsys inc

Application Engineer Senior (I)

Apr 2019 – Sep 2019 · 5 mos · Bengaluru, Karnataka, India · On-site

Owning ICC-II tool related issues and supporting two customers.
Involved in two tape-out projects for customer where I have given support for ICC-II.
Worked on 40nm and 7nm technology nodes for two customers.

ICC-II tool40nm technology7nm technologyApplication Engineering