Pavan Paladi

Software Engineer

Bengaluru, Karnataka, India8 yrs 9 mos experience

Highly Stable

Key Highlights

Expert in Physical Verification and ASIC Design.
Proficient in Synopsys Custom Compiler and Cadence tools.
Strong background in debugging and support for design teams.

Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in ASIC and Physical Verification.

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Skills

Core Skills

Physical VerificationAsic Design

Other Skills

Synopsys custom compiler toolCadence Virtuoso Layout EditorPDK QALinuxLayout Versus Schematic (LVS)ASIC FLOWICC toolprime time toolSTADesign Rule Checking (DRC)ANTENNA FIXINGDENSITY FIXINGCell Swap EcosMetal Ecos fixingRV violation Fixes

Experience

8 yrs 9 mos

Total Experience

3 yrs 2 mos

Average Tenure

2 yrs 4 mos

Current Experience

Synopsys inc

CAD Engineer

Feb 2024 – Present · 2 yrs 4 mos · Bengaluru, Karnataka, India · Hybrid

> Work closely with Mixed Signal IP development teams(Design & layout) for all PDKs/ flow/support issues.
> Debugged Physical Verification(DRC/LVS/DFM using ICV) issues related to runsets, tool.
> Provided support on Synopsys Custom Compiler platform for schematic & layout teams.
> Support for issues related to parasitic extraction(StarRC) and also electromagnetic extraction (Helic)
> Provided support on version control software related issues on project databases & also on grid, UNIX environment related issues. Also worked on Project environment Setup, documentation for customers.

Synopsys custom compiler toolCadence Virtuoso Layout EditorPDK QALinuxLayout Versus Schematic (LVS)ASIC FLOW+17