Pooja Kengnalkar

Lead IOS Developer

Bengaluru, Karnataka, India0 mo experience

Key Highlights

Expert in ASIC physical design and timing closure.
Proficient in using Synopsys tools for design verification.
Strong background in low-power design methodologies.

Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in ASIC physical design and timing analysis.

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Skills

Core Skills

Physical DesignTiming ClosureStatic Timing Analysis

Other Skills

Synopsys PrimetimeIC Compiler IITCL scriptingPrimeTimeRoot Cause AnalysisFailure Mode and Effects Analysis (FMEA)PowerplaningDesign for ManufacturingRoutingUnified Power Format (UPF)PlacementClock Tree SynthesisFloorplanSynopsys IC Compiler IILinux

Experience

0 mo

Total Experience

Average Tenure

Current Experience

Mediatek

Graduate apprenticeship trainee

Aug 2025 – Present · 10 mos · Benguluru · On-site

Rv skills design centre

ASIC Physical Design Engineer (Trainee)

Oct 2024 – May 2025 · 7 mos · Bengaluru, Karnataka, India · On-site

Title : SoC Block Level Implementation
Role: PD & Timing Closure
Tool : IC Compiler II - Synopsys
Description :
Designed a low-power, multi-voltage physical design block on 40nm technology, featuring dual supply voltages of 1.18V and 1.1V across 9 power domains.The design incorporated multi-Vt transistors, operated at a clock frequency of 1GHz, and occupied an area of approximately 4.52mm² with a gate count of around 0.4 million. Power budget limited to 450mW while maintaining IR drop within 5% of the supply voltage.
Challenges :
Macro placement involving pin orientation alignment and optimal connectivity to reduce routing detours and congestion.
Routing congestion and cell overlap issues encountered in high-density regions.
Achieving IR drop compliance through robust power mesh design and resolution of DRC violations within the power grid layout .
Multi-voltage errors due to missing level shifter strategies and associations, along with isolation strategy misconfigurations.
Debugging and implementing clock tree constraints for optimal clock distribution.
Improper clock tree construction occurred in shutdown domains where clock nets remained unbuffered despite the presence of always-on cells.
Managed signal routing complexities including DRC and LVS violations, antenna effect mitigation and redundant via insertion to ensure reliability.
Writing TCL scripts to automate guide buffer insertion, macro blockage.
2) Title: Analysis of the Timing Reports (STA)
Role: STA Engineer Tool: PrimeTime
Description :
Analyzed setup/hold slack for FF- and latch-based paths, including multi/half-cycle paths.
Applied OCV, CRPR, uncertainty, and handled false/multi-cycle path exceptions.
Debugged complex setup/hold violations in MCMM timing across corners.
Applied timing constraints using TCL scripting for multiple modes/corners.
Resolved clock skew, jitter, and path delays for timing closure.
Manually debugged critical paths unhandled by automated tools