Prakash Lakamanahalli

Product Engineer

Karnataka, India9 yrs 10 mos experience

Highly Stable

Key Highlights

Expertise in Physical Design and STA engineering.
Proficient in VLSI design methodologies.
Strong background in RTL to sign-off processes.

Stackforce AI infers this person is a VLSI Design Engineer with expertise in Physical Design and STA processes.

Contact

Skills

Core Skills

Physical DesignStaVlsi

Other Skills

ECORVPhysical verificationStandard cell layoutsLEF generationTECHLEF creationDRC rules validationAntenna rules validationPlace and route validationperl scriptingSKILL ScriptingCC++Perl AutomationMicroprocessors

About

I am working as Physical Design / STA Engineer Roles and Responsibilty : Complete APR (Fusion compiler) RTL to Sign off, STA, ECO, RV and Physical verification. Worked on 60nm to 18A nodes.

Experience

9 yrs 10 mos

Total Experience

5 yrs 1 mo

Average Tenure

4 yrs 9 mos

Current Experience

Intel corporation

SoC Design Engineer

Aug 2021 – Present · 4 yrs 9 mos · Bengaluru, Karnataka, India

STAPhysical DesignECORVPhysical verification

Sankalp semiconductor

3 roles

Physical Design Engineer

Promoted

Jul 2016 – Aug 2021 · 5 yrs 1 mo

Design Engineer

Jul 2016 – Nov 2018 · 2 yrs 4 mos

Roles and responsibilities :
1. Standard cell layouts : Layout architecture, Std cell layout from scratch and quality check.
2. LEF : Take care of LEF generation of the standard cell library and validate the LEF generated.
3. TECHLEF: Create technology LEF for libraries which includes DRC rules for different metal systems and validate the rules.
4. Validate antenna rules both in Cadence and innovus.
5. Basic place and route to validate technology LEF in Innovus. Place standard cells, route the metal system and validate connectivity, geometry and Antenna checks. OA out the design and clean LVS.

Standard cell layoutsLEF generationTECHLEF creationDRC rules validationAntenna rules validationPlace and route validation+2