Nov 2016 – Present · 9 yrs 6 mos · Bengaluru, Karnataka, India

• Led as Design Manager for E2E Panther Lake graphics die, successfully delivering A-step PRQ.
• Managing and leading Graphics Die end-to-end execution. Responsible for architecture-to-effort mapping , IP integration, subsystem integration and verification execution, IP selection and tracking (frontend and backend collaterals), UPF, DFD, DFT, power-aware and GLS simulation, tool checks (Lint, VCLP, CDC, FACT, Caliber), supporting the backend team for faster execution, governor milestone reviews, cross-functional and cross-geo team sync-up, and management weekly presentations.
• Responsible for project planning and milestone reviews, PXT, Mission Control communication, scheduling/micro-scheduling, resource management, competency development, team building/hiring, alignment with different stakeholders, continuous management reviews, and risk management.
• Delivered power chiplets (Patent filed) with high efficiency and zero silicon issues in A0 step. Responsible for project planning, SOC architecture, tech node IP office, custom IP development, SOC design and verification, SD support, and direct involvement in silicon bring-up.
• Leading global graphics, subsystem IP design and integration, power, reset, clocking, thermal telemetry, fabric implementation, DFD, RTL design, verification, and post-silicon activities through PRQ.
• Managing and leading power management PMC and DFD teams for SOC. Responsibilities include power PMC and DFD architecture, design execution, integration, PMC/DFD delivery schedule, and sync-up with SOC and pre-silicon software teams.

Sep 2014 – Nov 2016 · 2 yrs 2 mos · bangalore

• SoC Integration Lead
• Delivered Snapdragon SoCs as Integration SoC Lead, planning and executing RTL delivery for multiple integration milestones.
• Led hands-on integration of CPU, GPU cores, modem, analog IPs, DFT, etc., managing SoC flows including Lint, CDC, Synthesis, UPF, constraints, and Logic Equivalence checks.
• Awarded at Cadence CDNLive India 2015 for the paper “SLICE System – SoC Level Inter Connection Extractor”, whose methodology was later adopted in the Cadence Jasper tool and influenced competitor tools.
• SOC Power Architect
• Delivered power requirements and architecture for next-generation mobile SoCs, including board- and SoC-level power distribution and implementation of power-saving techniques.
• Defined methodologies for peak power estimation, power grid analysis, and next-generation mobile use cases.

Nov 2008 – Sep 2014 · 5 yrs 10 mos · Bangalore

• Modem IP Lead
• Design lead and architect for Modem top-level Clocking/Reset control and power controller across multiple Mobile SoC deliveries.
• Led integration of Processor subsystem, 2G/3G/LTE/TDSCDMA IPs — responsible for Modem system delivery to ASIC at 28nm HPM, including Lint, CDC, Synthesis, UPF, constraints, and Logic Equivalence flows.
• Power estimation for modem use cases and post-silicon power measurement for modem HW scenarios.
• Managed verification and post-silicon validation of the modem across multiple phases.
• Modem IP Power, Clock & Reset Architect
• Drove Modem 4G SoC power strategy, uArch, and implementation — designed clock tree, power-saving sleep modes (multiple states), and DVFS strategy for next-generation modem IP versions.
• Proposed and implemented new Power saving features and clocking modes; synced with SW team for proper integration and future use.
• Resolved post-silicon and customer issues related to power and clocking through debug and root-cause analysis.
• Power Estimation & Measurement Lead for product
• Led power estimation/measurement sub-group across multiple Nokia Modem IP deliveries; created modem power estimations for various use cases.
• PTPX-based power estimation for RTL and emulation (SW FSDB flows).
• Drove post-silicon SW team use-case scenario-based power reduction efforts.
• Silicon Validation Lead for India Site
• Established and built the Silicon Validation Lab at Nokia Modem India site — first-time setup of equipment, test board wakeup, and validation flow methodology.
• Led modem HW silicon validation: functional validation, power measurement, and technology bring-up; developed team capability for ongoing validation.

Mar 2004 – Oct 2007 · 3 yrs 7 mos · Bengaluru, Karnataka, India · On-site

• Clock and Reset module Owner
• Owned and drive Clock Controller design and validation as a Part of TI team working on Nokia Mobile phone SOC products
• Power characterizing of SOC
• Delivered 20x improvement in silicon validation execution, implemented new flow methodology.

Mar 2003 – Feb 2004 · 11 mos · Bangalore

• EPS (Electric Power Steering) Design
• I was responsible for the translation of specification into block diagram, hardware designing, component procurement, manufacturing, system integration, field testing and acceptance.
• HFMT (Hands Free Mobile Telephone) Design