Ratnesh Mohan

Software Engineer

Bengaluru, Karnataka, India2 yrs 6 mos experience

Most Likely To Switch

Key Highlights

Expert in Static Timing Analysis and synthesis.
Proficient in automation using Tcl and Perl.
Focused on scalable SoC design and AI hardware systems.

Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in SoC architecture and automation.

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Skills

Core Skills

Static Timing AnalysisSynthesis

Other Skills

PerlTCLSTASDC validationDebuggingSynopsys toolsConformal LECPhysical aware SynthesisConformal Low PowerCLaTeX

About

I am a Senior SoC Design Engineer with expertise in STA, synthesis, and back-end signoff at subsystem and SoC levels. I work on MVDD SoC timing, SDC validation, and debugging timing issues across DVFS scenarios. I focus on timing closure, constraint quality, and overall flow robustness. I also build automation using Tcl, Perl, and tcsh to improve QoR tracking and tool efficiency. Key work areas: • SoC STA and timing closure • SDC validation and constraint debugging • Subsystem synthesis (QoR-driven) • Back-end checks (LEC, CLP, TVS) • Automation and flow development Skills: STA, Synthesis, Verilog, Tcl, Perl, tcsh, CPU/GPU architecture I am interested in scalable SoC design, automation-driven flows, and AI-focused hardware systems.

Experience

2 yrs 6 mos

Total Experience

1 yr 3 mos

Average Tenure

1 yr 11 mos

Current Experience

Mediatek

2 roles

Senior Engineer (SoC Design)

Jul 2024 – Present · 1 yr 11 mos · Bengaluru, Karnataka, India · On-site

My current role:
1. Maintain ownership and developing tcsh, perl and TCL scripts for various tools and utilities.
2. Synthesis for subsys with appropriate QoR strategy.
3. SDC sanity evaluation on SoC level.
4. Ownership of SoC MVDD STA settings.
5. Path analysis and debugging constraints of SoC STA sessions.
6. All BE QCs on subsys level netlist (LEC, CLP, TVS, etc.)

PerlTCLStatic Timing AnalysisSynthesis