Saroja Biradar

Software Engineer

Bengaluru, Karnataka, India4 yrs 9 mos experience

Highly Stable

Key Highlights

7.5 years of experience in SoC building and PV Signoff.
Expertise in multiple technology nodes including 22nm and 16nm.
Strong project management skills in semiconductor design.

Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in SoC and VLSI technologies.

Contact

Skills

Core Skills

System On A Chip (soc)Project ManagementPhysical Design EngineeringLayout EngineeringVery-large-scale Integration (vlsi)

Other Skills

SoC PV Signoff22nm GF16nm/28nm TSMC technologyInnovusVirtuosoCalibredrv toolsCustom cell creationSVRF runset writingTCLshell scriptingBump planningPAD ring closureBond PAD placementintegration of third party IPCustom PG

About

7.5 years of experience in SoC building and PV Signoff. Currently working at Mediatek on SoC PV Signoff.

Experience

4 yrs 9 mos

Total Experience

3 yrs 6 mos

Average Tenure

1 yr 3 mos

Current Experience

Mediatek

Staff Engineer

Mar 2025 – Present · 1 yr 3 mos · Bengaluru, Karnataka, India · On-site

SoC PV Signoff, Project Management.

SoC PV SignoffProject ManagementSystem on a Chip (SoC)

Analog devices

2 roles

Physical Design Engineer

Promoted

Sep 2021 – Mar 2025 · 3 yrs 6 mos · On-site

Work experience on 22nm GF, 16nm/28nm TSMC technology node. Hands on experiences on Innovus, Virtuoso, Calibredrv tools. Custom cell creation, SVRF runset writing, TCL, shell scripting. Responsible for SoC and digital block PV signoff. Bump planning, PAD ring closure, Bond PAD placement, integration of third party IP at SoC level by meeting spec, Custom PG, BUMP/RDL routing. My role also includes collaboration with AMS team to get the ESD, PERC, DRC, LVS issues resolved which are seen at SoC, Timing ECO fixes, critical net re-routing and training new joinees.

22nm GF16nm/28nm TSMC technologyInnovusVirtuosoCalibredrv toolsCustom cell creation+20

Layout Engineer

Sep 2017 – Sep 2021 · 4 yrs · On-site

Responsible for custom std cells, macro creation in different technology nodes, which are successfully implemented at Fullchip. Hands on experiences in SVRF script writing and modifications, PG mesh creation at chip level, Analog macro integration and power hookups, RDL routing. Resistance extraction, clock routing with coaxial shielding.

custom std cellsmacro creationSVRF script writingPG mesh creationAnalog macro integrationpower hookups+5