Shaileshkumar B D

Software Engineer

Bengaluru, Karnataka, India19 yrs 11 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Expert in Design for Testability and Silicon Bringup.
Proven leadership in complex SOC verification processes.
Strong background in scan implementation and formal verification.

Stackforce AI infers this person is a Semiconductor Design Engineer specializing in DFT and verification processes.

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Skills

Core Skills

DftSilicon BringupScan ImplementationFormal VerificationMemory TestingAtpg

Other Skills

Project planningDebuggingDRC analysisCoverage analysisBoundary ScanShell scriptingPerl scriptingMemory Algorithm codingField-Programmable Gate Arrays (FPGA)Design EngineeringLeadershipVLSIEDABISTTest Automation

About

DFX - Comprehensive support from Pad selection for testing to silicon bring-up and customer debug assistance. DFX Design Implementation, Verification, and Silicon Bring-up - encompassing planning, leadership, and delivery. Cross-team interactions: Engaging with RTL Design, PAD Design, Clock Design, Timing, Synthesis, PNR, and PD Synthesis teams.. etc...

Experience

19 yrs 11 mos

Total Experience

5 yrs

Average Tenure

15 yrs 4 mos

Current Experience

Nvidia

Sr DFT Engineer

Jan 2011 – Present · 15 yrs 4 mos · Bengaluru, Karnataka, India · Hybrid

Design for Testability- DFX:
Test planning, implementation, and execution for SOCs & IPs
Setting up verification flow and optimizing processes for Complex SOCs
Development and optimization of flows, targets, and resources
Handling SCAN, MBIST, JTAG, ATPG, and Clocks at both RTL and gate levels with Silicon Bringup
Silicon bring-up planning and debuggin

Project planningSilicon BringupDFTATPGDebugging

Transwitch

MTS

Sep 2010 – Jan 2011 · 4 mos

Scan Implementation, Wrapper and Compression Implementation
Formal verification
DRC analysis (SCAN and ATPG)
> Coverage analysis

Scan ImplementationFormal verificationDRC analysisCoverage analysis

With texas instruments - from sasken

2 roles

Senior Design Engineer

Promoted

Jun 2008 – Sep 2010 · 2 yrs 3 mos

 Scan implementation,, DRC analysis, compression planning, clock analysis and inserting SCAN design with ATPG
 ATPG for stuck-at, Transition, Path Delay and IDDQ with DRC analysis
 Test-Coverage analysis and improvement, DRC analysis
 Memory Testing implementation using BIST [MBIST/PBITS/CPUBIST]
 Memory Algorithm coding: Based on mem type, need based & silicon issue debug based
 Memory Retention/Repair algo. Implementation with physical memory Understanding
 Experience with RTL/gate level simulation
 Boundary Scan and P1500 Knowledge
 Formal Verification (LEC)
 Shell, Perl scripting & Assembly languages