VENKATESH CHAVADEKAR

Software Engineer

Bengaluru, Karnataka, India7 yrs 10 mos experience
Highly Stable

Key Highlights

  • Expert in Physical Design for ASICs and SoCs.
  • Proven track record in timing closure and clock tree synthesis.
  • Strong analytical skills with extensive tool proficiency.
Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in ASIC and SoC physical design.

Contact

LinkedIn

Skills

Core Skills

Physical DesignApplication-specific Integrated Circuits (asic)Clock Tree Synthesis

Other Skills

Analytical SkillsTkinterKnowledge AcquisitionLayout Versus Schematic (LVS)Place and RouteSynopsys toolsDesign Rule Checking (DRC)Fusion CompilerInnovus(Design Implementation)PrimetimePhysical Verification (Calibre)Static Timing AnalysisRed Hat LinuxPython (Programming Language)System on a Chip (SoC)

Experience

7 yrs 10 mos
Total Experience
7 yrs 10 mos
Average Tenure
7 yrs 10 mos
Current Experience

Qualcomm

3 roles

Senior Lead Engineer

Promoted

Nov 2024 – Present · 1 yr 6 mos

Analytical SkillsTkinterKnowledge AcquisitionClock Tree SynthesisLayout Versus Schematic (LVS)Place and Route+15

Senior Physical Design Engineer

Nov 2020 – Nov 2024 · 4 yrs

  • SubHM PD Implementation with Timing closure for Image Front end engine for High end snapdragon (MSM) Chipsets, Custom Clock Tree Implementation(H-Tree, Fishbone Structure), Automating Sign Off checks.
Clock Tree SynthesisLayout Versus Schematic (LVS)Physical Design

Physical Design Engineer

Jul 2018 – Nov 2020 · 2 yrs 4 mos

  • Sub HM Level PD Implementation of Camera Sub Systems, multiple clocks with High frequency.
Synopsys toolsDesign Rule Checking (DRC)Physical DesignApplication-Specific Integrated Circuits (ASIC)

Education

National Institute of Technology Tiruchirappalli

VLSI SYSTEMS

Jan 2016 – Jan 2018

U B D T College of engineering

Bachelor’s Degree — Electronics and Communications Engineering

Jan 2010 – Jan 2014

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