Wei-Chih Liu

Software Engineer

Hsinchu City, Taiwan17 yrs 7 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Expert in physical design and static timing analysis.
Led multiple CAD initiatives at top tech companies.
Strong background in CPU and GPU design methodologies.

Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in Physical Design and CAD methodologies.

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Skills

Core Skills

Physical DesignStatic Timing AnalysisCadCpu DesignImplementationGpu DesignPpaSignoff FlowSoc Design

Other Skills

Physical Design PlatformCode DevelopmentCICD InfrastructureParasitic ExtractionECO FlowsFull-chip STA ExecutionCAD LeadPhysical Design FrameworkDK/PDK Release FrameworkCortex-A CPU ImplementationOoO ValidationGPU ImplementationPPA MethodologyTSMC 10nm Process BenchmarkIntegrated Signoff Flow System

Experience

17 yrs 7 mos

Total Experience

3 yrs

Average Tenure

3 yrs 9 mos

Current Experience

Rivos inc.

Principal Member Of Technical Staff

Aug 2022 – Present · 3 yrs 9 mos · Taiwan · On-site

1. Chef architect of physical design platform
2. Chef architect of code development/documentation/CICD infrastructure for CAD team
3. Chef architect of DK/PDK installation platform
4. Leader of physical design dashboard system
5. Owner of Parasitic Extraction, Static Timing Analysis, and ECO flows
6. Owner of Full-chip level STA execution and delivery

Physical Design PlatformCode DevelopmentCICD InfrastructureParasitic ExtractionStatic Timing AnalysisECO Flows+2

谷歌

Silicon CAD and infra

Jul 2018 – Aug 2022 · 4 yrs 1 mo · Taipei

1. CAD lead for PD, RTL, and DV domains
2. Chef architect of end2end physical design framework
3. Chef architect of DK/PDK release framework

CAD LeadPhysical Design FrameworkDK/PDK Release FrameworkPhysical DesignCAD

Arm

Staff Application Engineer

Jul 2016 – Jul 2018 · 2 yrs · Hsinchu

1. Cortex-A CPU implementation training and bring-up
2. Cortex-A CPU PPA with advanced technology
3. Cortex-A CPU OoO validation for implementation flow

Cortex-A CPU ImplementationPPAOoO ValidationCPU DesignImplementation

Huawei technologies

Senior Engineer

Jan 2016 – Jul 2016 · 6 mos · Hsinchu

1. Kirin 950 GPU implementation PPA methodology
2. Kirin 960 GPU implementation PPA methodology
3. TSMC 10nm process benchmark

GPU ImplementationPPA MethodologyTSMC 10nm Process BenchmarkGPU DesignPPA

Apple

Contractor

Sep 2013 – Dec 2014 · 1 yr 3 mos · San Jose

1. PPA for SoC blocks
2. CPU implementation and PPA
3. CPU signoff flow development
4. IP qualification utilities development

PPA for SoC BlocksCPU ImplementationSignoff Flow DevelopmentSoC DesignCPU Design

Tsmc

Section Manager

Oct 2008 – Jan 2016 · 7 yrs 3 mos · Hsinchu City, Taiwan, Taiwan

1. Integrated Signoff Flow System Development for advanced process
2. N10 test chip physical implementation.
3. Customer support on N16FF process physical implementation and N10/N16FF flow development
4. Tape-out review system development

Integrated Signoff Flow SystemPhysical ImplementationCustomer SupportSignoff FlowPhysical Design