Mehul Patel

Software Engineer

Bengaluru, Karnataka, India13 yrs 4 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Expertise in DFT methodologies and tools.
Strong background in MBIST and JTAG implementations.
Proven track record in silicon bring-up processes.

Stackforce AI infers this person is a DFT Engineer specializing in semiconductor testing and verification.

Contact

Skills

Core Skills

MbistDftAtpgJtag

Other Skills

ASICAssertion Based VerificationAssertionsBISTBlock level scan stitchingBoundary scan simulationCC++DebuggingFormal VerificationMBIST Pattern re-targeting using iJTAGMBIST VerificationNCSimPattern generationPerl Script

About

Experienced DFT Engineer with a demonstrated history of working in the semiconductors industry. Working knowledge of Scan, ATPG, iJTAG (IEEE 1687), MBIST, Simulation, Silicon bring-up. Strong engineering professional with a Master of Technology (M.Tech.) focused in VLSI Design from Nirma University, Ahmedabad.

Experience

Nxp semiconductors

DFT Principal Engineer

Aug 2022 – Present · 3 yrs 7 mos · India

Qualcomm

Staff Engineer

Aug 2021 – Jul 2022 · 11 mos · Bangalore Urban, Karnataka, India

Intel corporation

DFT Engineer

May 2018 – Aug 2021 · 3 yrs 3 mos · Bangalore

MBIST Verification
MBIST Pattern re-targeting using iJTAG (IEEE - 1687)
MBIST verification at IP level
MBIST Tester Pattern Delivery For complete IP
Actively involved in Silicon bring up for MBIST vectors
Working knowledge of ICL/PDL (iJTAG IEEE 1687)

MBIST VerificationMBIST Pattern re-targeting using iJTAGSilicon bring upMBISTDFT

Synopsys inc

2 roles

Sr. DFT Engineer

Nov 2017 – Apr 2018 · 5 mos

Supporting Synopsys DFT Solutions world wide (Onsite/Offsite)
 Scan Insertion: DFT Compiler
 Scan Compression: DFTMAX, DFTMAX Ultra
 ATPG: TetraMAX
 SpyGlass DFT

Scan InsertionScan CompressionATPGSpyGlass DFTDFT

DFT Engineer

Jul 2015 – Oct 2017 · 2 yrs 3 mos

Marvell semiconductor

DFT Consultant

Nov 2013 – May 2015 · 1 yr 6 mos · Bangalore, India

Worked on
Block level scan stitching in Hierarchical DFT architecture.
EDT insertion using TestKompress
Pattern generation using TestKompress (Mentor ATPG tool)
Pattern simulation (timing and no-timing) using VCS
Boundary scan simulation
Analog loopback test of SerDes BIST using JTAG.
PLL frequency lock test using JTAG.
DRO (Debug Ring Oscillator) testing using JTAG
IOMUX verification
OCC verification

Block level scan stitchingPattern generationBoundary scan simulationDFTJTAG

Sicon design technologies pvt. ltd.

DFT Engineer

Jun 2013 – Jun 2015 · 2 yrs · Bangalore

Worked as DFT engineer
Scan Chain Insertion using RTL Compiler of Cadence
Scan Compression and power aware scan insertion
Pattern generation using Encounter Test of Cadence
MBIST using Tessent of Mentor
JTAG - Boundary Scan insertion and simulation using Tessent of Mentor

Scan Chain InsertionScan CompressionPattern generationMBISTJTAGDFT

Stmicroelectronics

Intern

Jun 2012 – May 2013 · 11 mos · Greater Noida

Worked with DFT Team in Automotive Product Group at STMicroelectronics. Having experience of
Scan chain insertion using DFT compiler
Pattern generation using TMAX
Test Mode Entry pattern debugging
Assertion Based Verification using Incisive Formal Verifier tool for IOPADs and DFT like BIST connectivity etc..
Functional verification of Multi Timer Unit (IP).
Perl Scripting to generate pmap file from xml file and generate assertion for formal verification
Also having basic knowledge of DFT concept like
Automatic Test Pattern Generation (ATPG)
MBIST Flow
JTAG - Boundary Scan
Scan Design
Fault Models
Tools known:
DFT Compiler and TetraMAX of Synopsys
NCSim, RTL Compiler and Incisive Formal Verifier of Cadence
Scripting Languages:
Good working knowledge of Perl
Tcl