S

Suman Halder 🇮🇳

Software Engineer

Bengaluru, Karnataka, India5 yrs experience
Most Likely To Switch

Key Highlights

  • Expert in low-power design and verification methodologies.
  • Proficient in System Verilog and UVM for functional verification.
  • Hands-on experience in RTL coding and digital design.
Stackforce AI infers this person is a Semiconductor and Aerospace verification engineer with expertise in RTL and UVM methodologies.

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Skills

Core Skills

Lpddr5Universal Verification Methodology (uvm)Lpddr4C++System VerilogFunctional VerificationRtl Coding

Other Skills

AMBAAMBA AHBAPBAXIAssertion Based VerificationCC (Programming Language)Engineering DocumentationGatesimLow-power DesignLpddrNumPyPerlPython (Programming Language)RTL Design

About

Qualcomm:: working as a senior design verification engineer for low power lpddr5 domain Bitsilica Pvt limited : worked on UVM based test bench for SPI Ip and also written SVA for AXI4, also developed RTL code for satellite data acquisition system parallely developed a sv based testbench components for the design Soctronics Pvt limited: worked as Engineer 1 in Functional Verification domain at Soctronics( AMD-ODC) ,Hyderabad *Have good knowledge in RTL coding,Verification ,System Verlilog,VHDL coding,FPGA coding. *Have basic knowledge in CMOS,Digital VLSI *Have a good knowledge in Digital design circuits *Method oriented language known - c *Object oriented language known java,c++ *Shell scripting language known Unix,perl,TCL

Experience

Qualcomm

3 roles

Senior Design Verification Engineer

Dec 2023 – Present · 2 yrs 3 mos

LPDDR5UPFUniversal Verification Methodology (UVM)TCLUnixPerl+10

Design verification Engineer 3(client) via Mirafra

Oct 2021 – Dec 2023 · 2 yrs 2 mos

UPFLPDDR4UnixPerlGatesimLow-power Design+8

Design verification Engineer 2(client) via Mirafra

Jul 2020 – Oct 2021 · 1 yr 3 mos

C++UPFLPDDR4PerlGatesimLow-power Design+12

Bitsilica private limited

Senior RTL Design and Verification Engineer

Mar 2020 – Jul 2020 · 4 mos · Work from Home · Remote

  • worked on UVM based test bench for SPI Ip and also written SVA for AXI4, also developed RTL code for satellite data acquisition system parallely developed a sv based testbench components for the design
AMBAAssertion Based VerificationAPBEngineering DocumentationSystem VerilogFunctional Verification+6

Amd

2 roles

SoC Verification/Validation Engineer 1(client) via Soctronics

Promoted

Apr 2019 – Mar 2020 · 11 mos · On-site

Engineering Documentation

SoC Verification/validation Engineer trainee(client) via Soctronics

Apr 2018 – Mar 2019 · 11 mos · On-site

  • Currently working on DV and DV Flow
PerlGatesimAMBAUniversal Verification Methodology (UVM)CAssertion Based Verification+9

Veda iit

Post Graduate Diploma in Logic design domain sponsored by Soctronics

Jul 2017 – Jan 2018 · 6 mos · Hyderabad, Telangana, India

  • Learned topics like
  • 1. System Verilog
  • 2. Static timing Analysis
  • 3. RTL Verification methodologies
  • 4. RTL design
  • 5. Advance C
  • 6 . C++
  • 7. PERL
  • 8. UNIX
  • 9.TCL

Indian railways

Vocational trainee on Signal and Telecommunication

Jan 2016 – Jan 2016 · 0 mo · Sealdah, kolkata

  • Learned basics of
  • 1. OFC communication
  • 2. ISDN Exchange
  • 3. Rajdhani Express communication
  • 4. Train Induction Board
  • 5. Surveillance System
  • 6.IPDSLAM
  • 7.Public Amenity System
  • 8. IP Exchange

Central tool room & training centre (msme) government of india

2 roles

Vocational trainee on Embedded system

Jul 2015 – Jul 2015 · 0 mo · Kolkata, West Bengal, India

Vocational Trainee on VLSI

Jun 2015 – Jul 2015 · 1 mo · Kolkata, West Bengal, India

Globsyn technologies

Vocational trainee on JAVA 8

Dec 2014 – Jan 2015 · 1 mo · Kolkata, West Bengal, India

Education

Jalpaiguri Government Engineering College

Bachelor of Technology (B.Tech.) — electronics and communication engineering

Jan 2013 – Jan 2017

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