Arjun Singh

DevOps Engineer

Noida, Uttar Pradesh, India13 yrs 8 mos experience

Highly StableAI Enabled

Key Highlights

Led a team of 10 engineers for AI accelerator verification.
Expert in full verification lifecycle from planning to sign-off.
Pioneered GenAI integration for verification tasks.

Stackforce AI infers this person is a Semiconductor Verification Expert with a focus on AI/ML technologies.

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Skills

Core Skills

Functional VerificationFormal VerificationArtificial Intelligence (ai)

Other Skills

ARM Cortex-MASICAssembly LanguageCC++DebuggingFPGAFormal LanguagesHDMIPerlPerl ScriptPython (Programming Language)RISC-VSystem VerilogTime Management

About

Accomplished Verification Leader with 13+ years of experience in delivering high-quality verification for complex subsystems and IPs across multiple technology domains, including AI/ML, image processing, multimedia, graphics, and networking. • Proven leadership: Led a team of 10 engineers to verify a scalable AI accelerator from concept to sign-off, delivering compute capabilities from hundreds of GigaOPs to multi-TeraOPs for multiple SoCs. • Full verification lifecycle expertise: Skilled in all phases from test planning to coverage-driven verification sign-off. • GenAI integration: Hands-on in applying Generative AI for verification tasks such as test planning, creation of testbench components, checkers, assertions, and debugging. • Technical strengths: Deep expertise in SystemVerilog, UVM, and formal verification. • Processor & subsystem verification: Extensive experience with RISC-V and ARM Cortex-based subsystems, high-speed interconnects (CHI, ACE, AHB, AXI, Ethernet, HDMI, MHL), and performance verification at IP and subsystem level. • Notable projects: Led verification of a Neural Processing Unit (NPU) from scratch, ensuring first-time-right silicon. Passionate about driving verification innovation, leveraging GenAI for productivity gains, and delivering robust, scalable solutions for cutting-edge SoCs.

Experience

Microsoft

Senior Design Verification Engineer

Dec 2024 – Present · 1 yr 3 mos · Noida, Uttar Pradesh, India · On-site

Functional VerificationFormal VerificationVerification using gen AI

Nxp semiconductors

3 roles

Sr Staff Verification Engineer

Promoted

Apr 2022 – Dec 2024 · 2 yrs 8 mos · Noida, Uttar Pradesh, India

Lead Verification of AI/ML HW accelerator development from scratch and delivered to multiple SOC programs for specific compute requirements ranging from hundreds of GOPS to few TOPS and different integration requirements.

RISC-VArtificial Intelligence (AI)Formal VerificationFunctional VerificationTime Management

Staff Design Engineer

Nov 2019 – Mar 2022 · 2 yrs 4 mos · Noida, Uttar Pradesh, India

Leading verification planning and efforts at IP and subsystem level for Neural Network Processing engine and Communication engine for NXP's automotive SOC.

Lead Design Engineer

May 2017 – Sep 2018 · 1 yr 4 mos · Noida Area, India

Worked on verification of part of NXP's ADAS solution chips. Which will be used to build next generation self driving cars. Working on image processing IP, which extract features from input image for object detection.

Intel corporation

Pre silicon verification engineer

Sep 2018 – Nov 2019 · 1 yr 2 mos · Bengaluru, Karnataka, India

I was part of SOC verification team for there graphics processor card for server domain. I was leading verification of fabric subsystem at both subsystem and soc level. I was involved complete verification cycle.

Solarflare communications

Asic Verification Engineer

Mar 2014 – May 2017 · 3 yrs 2 mos · New Delhi

At Solarflare I worked on verification of High Speed Network Controller using UVM based TB's. I was part of teams responsible for verification FPGA based and ASIC products. Worked on various parts of there solutions like descriptor loader, Transmit Datapath, Pacer, solar capture upstream Datapath etc.

Inde-sys

Associate Engineer

Sep 2013 – Feb 2014 · 5 mos · New Delhi Area, India

Client: Solarflare I worked on verification of High Speed Network Controller using UVM based TB's. I was part of teams responsible for verification FPGA based and ASIC products. Worked on various parts of there solutions like descriptor loader, Transmit Datapath, Pacer, solar capture upstream Datapath etc.

Transwitch

Associate Engineer

May 2012 – Aug 2013 · 1 yr 3 mos · New Delhi Area, India

Verification Environment development using system verilog and VMM.
Perl scripting to automate various process.
Worked on standards like HDMI & MHL. Worked on various parts of there high speed interconnects devices like MHL TX tmds, control sub system, Register spec. Etc.