M

Mallikarjuna .

Product Engineer

Bengaluru, Karnataka, India2 yrs 5 mos experience

Key Highlights

  • Trainee in VLSI Design and Verification.
  • Strong foundation in Electronic Engineering.
  • Proficient in multiple programming languages.
Stackforce AI infers this person is a VLSI Design and Verification Trainee with a focus on semiconductor technology.

Contact

LinkedIn

Skills

Core Skills

Vlsi DesignVerification

Other Skills

AMBAAnalog SemiconductorsC (Programming Language)CMOSCommunicationDigital DesignsDigital ElectronicsElectronic Circuit DesignElectronic EngineeringEmbedded CEmbedded SystemsJavaMATLABMicrocontrollersObject-Oriented Programming (OOP)

Experience

Maven silicon

VLSI Design and Verification trainee

Oct 2023 – Present · 2 yrs 5 mos · Bangalore · Remote

VLSI DesignVerificationSystemVerilogRTL DesignUVM

Education

Ramaiah Institute Of Technology

Bachelor of Engineering - BE

Jan 2019 – Aug 2023

Stackforce found 100+ more professionals with Vlsi Design & Verification

Explore similar profiles based on matching skills and experience

DK

Dr. Vandana Khanna

Dy dean (PhD)

at The NorthCap University

Gurgaon, India22 yrs 9 mos exp
Nidhi Gupta

Nidhi Gupta

VLSI Intern V | ASIC Verification, UVM Testbench Development, and RTL Verification

at Seagate Technology

Hillsboro, United States13 yrs 2 mos exp
SoC VerificationUVM
Deepti Dewangan

Deepti Dewangan

Senior Engineer

at Qualcomm

India3 yrs 6 mos exp
Ajinkya Kautikwar

Ajinkya Kautikwar

Applications Engineer II

at Synopsys Inc

Yavatmal, India4 yrs 10 mos exp
Nilesh Pathrabe

Nilesh Pathrabe

Accumulated Expertise

at Career-Wide Experience

Nagpur, India0 mo exp
RS

Rajesh S.

Verification Engineer

at Youzentech Technologies

Bangalore Urban, India14 yrs 3 mos exp
Digital ElectronicsVerification
SRI RAMA KRISHNA KAUSHIK VARANASI

SRI RAMA KRISHNA KAUSHIK VARANASI

Senior Design Engineer 1

at Microchip Technology Inc.

Hyderabad, India8 yrs 5 mos exp
Complex Programmable Logic Device (CPLD)Coverage Analysis
Devesh Kumar

Devesh Kumar

Principal Design Engineer

at Cadence Design Systems

Delhi, India14 yrs 9 mos exp
Functional VerificationOpen Verification MethodologySystemVerilogVHDLVMM