Priyanka Pandey

Software Engineer

Bengaluru, Karnataka, India4 yrs 11 mos experience
Highly Stable

Key Highlights

  • Expertise in lower power design nodes.
  • Hands-on experience with Synopsys tools.
  • Strong foundation in ASIC flow and digital circuits.
Stackforce AI infers this person is a VLSI design engineer with a focus on ASIC development and digital circuit design.

Contact

LinkedIn

Skills

Core Skills

Static Timing AnalysisRtl Design

Other Skills

RTL CodingTCLC (Programming Language)VerilogSystemVerilogUniversal Verification Methodology (UVM)Application-Specific Integrated Circuits (ASIC)Skilled Multi-taskerProblem SolvingTeam Leadership

About

- Experience in lower power design nodes and various design like 32nm , 90nm and 180nm. • Strong understanding of ASIC flow and STA. • Good Knowledge of RTL Coding. • Having hands-on experience in Synopsys tools : VCS , Design Compiler , Prime time , ICC. • Good understanding of scripting language : TCL. • Sound Knowledge of Digital Circuits and CMOS. • Hands - on knowledge of C programming.

Experience

4 yrs 11 mos
Total Experience
4 yrs 11 mos
Average Tenure
4 yrs 11 mos
Current Experience

Mediatek

Synthesis and STA Engineer

May 2021 – Present · 4 yrs 11 mos

Static Timing AnalysisRTL DesignRTL CodingTCLC (Programming Language)

Vlsiguru training institute

Trainee

Sep 2019 – Feb 2020 · 5 mos

Indian institute of technology, bombay

Summer Internship

Feb 2015 – Jul 2015 · 5 mos · Mumbai, Maharashtra, India

  • Summer Internship (CISC Processor) under the guidance of Dr. Virender Singh, Electrical Engineering Department, IIT Bombay.

Education

Vellore Institute of Technology

Master of Technology - MTech — VLSI design

Jan 2017 – Jan 2019

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Priyanka Pandey - Software Engineer | Stackforce