Jan 2016 – Oct 2018 · 2 yrs 9 mos · Bengaluru Area, India

• My responsibilities included creating and implementing test benches using UVM methodology, developing test cases, and analyzing simulation results to ensure that the memory subsystems met all specifications and design requirements.
• I collaborated closely with the design team to identify and resolve any issues that arose during the verification process. This required strong communication skills and the ability to work collaboratively to ensure that the memory subsystems were optimized for performance and reliability.
• Additionally, I utilized my expertise in System Verilog to develop complex verification environments that could test the memory subsystems in a variety of scenarios. I also conducted coverage analysis and created reports to track the progress of the verification process.

Jan 2016 – Oct 2018 · 2 yrs 9 mos · Bengaluru Area, India

May 2015 – Jan 2016 · 8 mos · Bengaluru Area, India

• My work involved utilizing my expertise in hardware description languages such as VHDL and Verilog.
• I was responsible for developing formal test benches and test cases to ensure that the PowerPC core met all specifications and design requirements. This required an in-depth understanding of the core architecture and the ability to create complex verification environments to test the core under a variety of conditions.
• In addition, I collaborated closely with the design team to identify and resolve any issues that arose during the verification process. This required strong communication skills and the ability to work collaboratively to optimize the performance and reliability of the PowerPC core.

Feb 2014 – Mar 2015 · 1 yr 1 mo · Bengaluru Area, India

• Worked on Core logic verification

Oct 2012 – May 2014 · 1 yr 7 mos

• I led the formal verification activities for these blocks, which involved utilizing formal methods to verify the correctness of the design. This required an in-depth understanding of formal verification tools such as SixthSense and the ability to create formal properties and assertions to prove the correctness of the design.
• Furthermore, I worked closely with the design team to identify and resolve any issues that arose during the verification process. This required strong communication skills and the ability to work collaboratively to optimize the performance and reliability of the VSU and DFU blocks.

Jul 2011 – Sep 2012 · 1 yr 2 mos

• Formal/Functional verification on VSU and DFU block

Mar 2011 – Jun 2011 · 3 mos

Jun 2009 – Mar 2011 · 1 yr 9 mos · Nagpur Area, India

• During my Master's program, I had the opportunity to gain valuable teaching experience by instructing undergraduate Digital Design Lab and Basic Electronics Lab. I was responsible for designing and teaching laboratory sessions, developing hands-on activities, and grading lab reports. I worked closely with students to ensure that they understood the material and could apply it to real-world projects.
• In addition to teaching, I also had the opportunity to set the papers for Basic Electronics and Digital Circuits, two foundational courses in electrical and electronics engineering. As a paper setter, I was responsible for developing clear and concise questions that effectively tested students' understanding of the course material. I also reviewed papers submitted by students and provided detailed feedback on areas for improvement.